• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.336-339
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• 1995

There has been considerable interest in electrochromic devices because of its potential application in automobiles including mirrors and windows. The electrochromic(EC) mirror can automatically control the amount of glare produced by headlights or other light source on either inside or outside mirrors. Therefore, the EC mirror can be a better alternative to todays day-night mirrors for automobiles. In this paper we have fabricated all solid state EC mirrors with glass-ITO / a-WO$_3$/ polymer electrolyte / a-V$_2$O$\sub$5/ / ITO-glass / Al structure and investigated their spectral reflectance as a function of applied voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.423-427
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• 1998

In this paper the electron mobility in $Ga{1-X}In_xAs$alloy semiconductors is simulated by using the ensemble Monte Carlo method. The simulations for Ga\ulcornerIn\ulcornerAs with In mole fraction, doping concentration and temperature as parameters are performed. The electron mobility for alloys which perfectly orderd alloys without the alloy scattering mechanism are assumed, the results show that mobility in Ga\ulcornerIn\ulcornerAs is improved by 11%, 12% and 7% for 0.25, 0.53 and 0.75. In mole fractions, respectively, We reported the theoretical results of electron mobility in $Ga{1-X}In_xAs$alloys, so those will contribute to the research and development into materials for high-speed semiconductor devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.1-4
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• 1991

EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1073-1075
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• 2001

The nitrogen oxides, NO and NO2, abbreviated usually as NOx, emitted from combustion facilities such as power plants and automobiles are the typical air-pollutants causing acid rain and photochemical smog. In order to solve the NOx-related pollution problems effectively, we need efficient techniques to monitor NOx in the combustion exhausts and in environments. Development of solid-state electrochemical devices for detecting NOx is demonstrated based on various combination of solid electrolytes and auxiliary sensing materials. The object of this research is to develop various sensor performance for solid state amperometric sensor, and to test gas sensor performance manufactured. So we try to present a guidance for developing amperometric gas sensor. We concentrated on development of manufacturing process and performance test.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.139-142
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• 2001

As microeletronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important for many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (5-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.85-88
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• 1998

Light-emitting diode(LEDs), diode arrays, and phosphor display panels are finding increased use in a variety of commercial applications. Present and anticipated application of these devices include solid state indicator(e.g., digital clocks, meter readout) and display systems(e.g., instrument panels, TV display), the application being determined by the light -output capability and size availability(cost) of the particular device. In this work, Phosphor based on ZnS:Cu are used. Relation by luminance with the thickness of insulating layer and phosphor layer are discussed. Increased thickness of insulating layer are stable on voltage to 300V. By considering thickness and voltage, optimal structure and thickness are investigated. Also in order to maximize even surface emission, various sieving process are introduced. Very similar phosphor particle size is selected. Luminance by various wave intensity is also investigated. 150cd/m$^2$ luminance are investigated in stable voltage and frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.17-20
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• 1998

Thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystals was investigated by applying high temperature ($\geq$1100$^{\circ}C$) annealing and non-agitation Secco etching. For evaluation of the effect of LP upon device performance / yield, DRAM and ASIC devices were fabricated. The results indicate that high temperature annealing generates LPs whereas it decreases FPD density drastically, and LP does not have detrimental effects on the performance /

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.1
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• pp.1-6
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• 2004

Dry etch characteristics of polysilicon with HBr/O$_2$ inductively coupled plasma (ICP) have been investigated. We determined etch late, uniformity, etch profiles, and selectivity with analyzing the cross-sectional scanning electron microscopy images obtained from top, center, bottom, right, and left positions. The etch rate of polysilicon was about 2500 $\AA$/min, which meets with the mass production for devices. The wafer level etch uniformity was within $\pm$5 ％. Etch profile showed 90$^{\circ}$ slopes without notches. The selectivity over photoresist was between 2:1∼4.5:1, depending on $O_2$ flow rate. The HBr-ICP etching showed higher PR selectivity, and sharper profile than the conventional Cl$_2$-RIE.