• 한국전기전자재료학회논문지
• /
• 제21권4호
• /
• pp.289-295
• /
• 2008

In this paper, we designed the off-line PWM(Pulse width modulation) control IC for flyback type power converter to reduce the standby power consumption. In normal state, this off-line PWM IC generates the output pulse with $40\sim60kHz$ frequency and duty ratio of $20\sim88%$. When SMPS operates in standby mode, this IC generates the output pulse with 33kHz frequency and duty ratio of 1 %. SPICE simulation was performed to verify the standby power consumption of the power converter with designed of-line PWM IC. Power converter with designed off-line PWM IC consumes less than 0.3W when it operates in standby mode condition.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.1007-1008
• /
• 2006

This paper presents a optimal path search of mobile robot using energy efficiency. Proposed method has two goals that determining the velocity of mobile robot and finding the optimal path. We model the relationship of motors' speed and power consumption with quadratic polynomials. In order to verify the effectiveness of the proposed method, we performed simulations on the energy consumption of different paths.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.481-482
• /
• 2007

This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

• 한국전기전자재료학회논문지
• /
• 제16권7호
• /
• pp.634-640
• /
• 2003

This paper is to be researched into ozone generation character of Bi-Ti-Si type high dielectric yield ceramic catalyst discharge tube. And conditions of basic experiment are the outside diameter of discharge tube : 52 mm, the length of discharge tube : 350 mm, the frequence : 900 Hz, the temperature of cooling water : 25 $^{\circ}C$, quantity of flow : 5, 10, 20 l/min, pressure : 1.2, 1.4, 1.6 atm, and distance of discharge gap : 0.4, 0.6, 0.8 mm. Ozone generation characteristics were measured to consumption power. At quantity of flow : 20 l/min, discharge gap : 0.6 mm, pressure : 1.6, and consumption power : 150 W, Maximum ozone generation efficiency of 175 g/kWh was obtained. Maximum ozone generation efficiency was measured below the flow quantity of 20 l/min at below pressure of 1.6 atm. However, Maximum ozone generation efficiency was measured over the flow quantity of 20 l/min at over pressure of 1.6 atm.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.569-572
• /
• 2000

This paper presents the optimized fabrication and thermal characteristics of micro-heaters for thermal MEMS applications using a SDB SOI substrate. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10$\mu\textrm{m}$ thick silicon membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD(Resistance Thermometer Device)on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280$^{\circ}C$ at input Power 0.9 W; for the SOI membrane with 10 trenches, it is 580$^{\circ}C$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro thermal sensors and actuators.

• 센서학회지
• /
• 제33권3호
• /
• pp.134-138
• /
• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• 디지털융복합연구
• /
• 제14권9호
• /
• pp.309-315
• /
• 2016

무선 모바일 네트워크 환경에서 노드 이동성은 에너지 소모를 가중화시킨다. 본 논문에서는 노드 이동성으로 인한 에너지 소모를 줄이고, 클러스터 멤버 노드의 수명 주기를 연장시키기 위하여 클러스터 기반의 노드 관리 알고리즘 (CNMA: Cluster-based Node Management Algorithm)을 제안한다. 제안된 CNMA 알고리즘은 클러스터 내에서 클러스터 헤더 노드와 멤버 노드들의 이동성을 추적하고 이들의 관계를 주기적으로 모니터링함으로써 에너지 잔량을 분석한다. 그리고 노드들의 상태 전이 과정을 분석하여 클러스터링 분할과 병합을 수행한다. 본 연구의 목적은 노드 이동성으로 발생된 에너지 소모를 최소화하기 위한 것이다. 시뮬레이션 결과를 통하여 제안된 알고리즘이 이동성으로 인한 에너지 소모를 효율적으로 제어할 수 있음을 보이며, 에너지 수명 주기가 향상됨을 보인다.

• 대한전자공학회논문지SD
• /
• 제47권1호
• /
• pp.52-59
• /
• 2010

본 논문에서는 고해상도 및 고속 카메라용 column-wise Cyclic ADC 기반의 이미지 센서를 제안한다. 제안된 센서는 면적 및 전력 소모를 최소화 하기 위해 내부 블록에 사용되는 operational transconductance amplifier (OTA) 및 capacitor를 공유하는 기법을 사용하였다. 제안된 ADC는 QVGA급 화소의 이미지 센서로 프로토타입 칩을 제작하여 검증되었다. 측정결과, 최대 프레임 레이트는 120 fps 이며, 전력소모는 130 mW 이다. 전원 전압은 3.3 V가 공급되었고, 프로토타입은 $4.8\;mm\;{\times}\;3.5\;mm$의 실리콘 면적을 차지한다.

• 대한전자공학회논문지SD
• /
• 제45권1호
• /
• pp.43-49
• /
• 2008

본 논문에서는 Ant Colony Optimization(ACO)을 이용하여 Single-Error Correcting & Double-Error Detecting(SEC-DED)을 제공하는 메모리 ECC 체커 회로의 소비전력을 절감하는 방안을 제시한다. H-매트릭스를 통해 구현되는 SEC-DED 코드인 Hsiao 코드의 대칭성과 H-매트릭스 구성상의 높은 자유도를 이용하여 회로의 면적, 딜레이에 영향을 주지 않고 최소의 비트 트랜지션이 일어나도록 H-매트릭스를 최적화한다. 실험을 통하여 H-매트릭스의 최적화를 위한 ACO 매핑과 파라메터의 설정을 알아보고 이의 구현 결과를 랜덤 매트릭스 구성을 통한 방식 및 기존의 GA알고리즘을 이용한 최적화 방식과 비교하여 소비 전력이 기존의 방식에 비해 절감될 수 있음을 보여준다.

• Transactions on Electrical and Electronic Materials
• /
• 제16권5호
• /
• pp.241-249
• /
• 2015

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.