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High Frame Rate CMOS Image Sensor with Column-wise Cyclic ADC  

Lim, Seung-Hyun (Department of Electrical and Electronic Eng., Yonsei University)
Cheon, Ji-Min (Department of Electrical and Electronic Eng., Yonsei University)
Lee, Dong-Myung (Department of Electrical and Electronic Eng., Yonsei University)
Chae, Young-Cheol (Department of Electrical and Electronic Eng., Yonsei University)
Chang, Eun-Soo (Department of Electrical and Electronic Eng., Yonsei University)
Han, Gun-Hee (Department of Electrical and Electronic Eng., Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.1, 2010 , pp. 52-59 More about this Journal
Abstract
This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.
Keywords
Analog-to-digital converter; CMOS image sensor; cyclic ADC; high-definition TV; operational transconductance amplifier;
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