• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.215-220
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• 2012

Recently, one of the research topics is wireless Ad-Hoc network minimizing power consumption because of limited power. We propose optimal power allocation scheme of each transmit node and derive performance analysis of system that recently designed Double opportunistic relay system which fixed branch receiver to use more than efficient power consumption. Optimal power location scheme is shown that outage probability has always better performance than equal power allocation. Furthermore, we are known that outage probability is minimized by increasing average transmit relays to obtain the diversity gain when average channel power gain is less.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.431-437
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• 2012

PV simulators are essential equipment for testing power conditioning systems (PCS) which are one of an important part in PV generator systems, for testing before shipment. High dynamic PV simulator is required since MPPT(Maximum Power Point Tracking) test procedure has been established by EN50530 regulation recently. Most high quality PV simulator prevailed in the market is linear type which however has low efficiency. This paper proposes design guide lines for the power stage and LCL type filter cooperating with a switching mode PV simulator that shows high efficiency and very low power consumption. Proposed theory is verified by experiment.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5168-5181
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• 2017

The popularity of augmented reality (AR) applications and games are in high demand. Currently, the best common platform to implement AR services is on a smartphone, as online games, navigators, personal assistants, travel guides are among the most popular applications of smartphones. However, the power consumption of an AR application is extremely high, and therefore, highly adaptable and dynamic low power control schemes must be used. Dynamic voltage and frequency scaling (DVFS) schemes are widely used in smartphones to minimize the energy consumption by controlling the device's operational frequency and voltage. DVFS schemes can sometimes lead to longer response times, which can result in a significant problem for AR applications. In this paper, an AR response time monitor is used to observe the time interval between the AR image input and device's reaction time, in order to enable improved operational frequency and AR application process priority control. Based on the proposed response time monitor and the characteristics of the Linux kernel's completely fair scheduler (CFS) (which is the default scheduler of Android based smartphones), a response time step control (RSC) scheme is proposed which adaptively adjusts the CPU frequency and interactive application's priority. The experimental results show that RSC can reduce the energy consumption up to 10.41% compared to the ondemand governor while reliably satisfying the response time performance limit of interactive applications on a smartphone.

• ETRI Journal
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• v.28 no.6
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• pp.732-738
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• 2006

In this paper, novel CMOS pseudo-exponential circuits operating in a class-AB mode are presented. The pseudo-exponential approximation employed is based on second order equations. Such terms are derived in a straightforward way from the inherent nonlinear currents of class-AB transconductors. The cells are appropriate to be integrated in portable equipment due to their compactness and very low power consumption. Measurement results from a fabricated prototype in a 0.5 ${\mu}m$ technology reveal a range of 45 dB with errors lower than ${\pm}0.5$ dB, a power consumption of 100 ${\mu}W$, and an area of 0.01 $mm^2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.228-233
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• 2001

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro elelctro mechanical system) applications usign SOI (Si-on-insulator) and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10㎛ thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD (resistance thermometer device) on the same substrate by suing MgO as medium layer. The thermal characteristics of the micro-heater wit the SOI membrane is 280$\^{C}$ at input power 0.9W; for the SOI membrane with 10 trenches, it is 580$\^{C}$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.569-572
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• 2000

This paper presents the optimized fabrication and thermal characteristics of micro-heaters for thermal MEMS applications using a SDB SOI substrate. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10$\mu\textrm{m}$ thick silicon membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD(Resistance Thermometer Device)on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280$^{\circ}C$ at input Power 0.9 W; for the SOI membrane with 10 trenches, it is 580$^{\circ}C$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro thermal sensors and actuators.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.4
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• pp.491-497
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• 2015

In this paper a method of design and Implementation of RFID based control system for reducing standby power consumption at the power outlet is described. The system is composed of a RF controlled power outlet having relay and an active RFID tag communicating with the RF reader module controlling the relay. When the tag carried by human approaches to the RF reader the reader recognizes the tag and switch off the relay based on the RSSI level measurement. A low power packet prediction algorithm has been used to decrease the DC power consumption at both the tag and the RF reader. The result of experiment shows that successful operation of the relay control has been obtained while low power operation of the tag and the reader is achieved using above algorithm. Also setting the distance between the reader and the tag by controlling transmission power of the tag and adjusting the duty cycle of the packet waiting time when the reader is in idle state allows us to reduce DC power consumption at both the reader and the tag.

• Journal of Communications and Networks
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• v.18 no.4
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• pp.619-628
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• 2016

This paper describes a theoretical framework for rate allocation to maximize the power efficiency of overall heterogeneous wireless networks whose users are assumed to have multihoming capabilities. Therefore, the paper first presents a power consumption model considering the circuit power and radio transmission power of each wireless network. Using this model, two novel power efficient rate allocation schemes (PERAS) for multihoming services are proposed. In this paper, the convex optimization problem for maximizing the power efficiency over wireless networks is formulated and solved while guaranteeing the required quality of service (QoS). Here, both constant bit rate and variable bit rate services are considered. Furthermore, we extend our theoretical framework by considering the sleep-operation management of wireless networks. The performance results obtained from numerical analysis reveal that the two proposed schemes offer superior performance over the existing rate allocation schemes for multihoming services and guarantee the required QoS.

• Journal of Sensor Science and Technology
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• v.12 no.6
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• pp.231-240
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• 2003

The problem of power consumption and the limitation of a chip area should be considered when the pixel number of the edge detection circuit increases to fabricate a vision chip for edge detection with high resolution. The numeric increment of the unit circuit causes power consumption to increase and require a larger chip area. An increment of power consumption and a limitation of chip area with several ten milli-meters square supplied by the CMOS foundry company restrict the pixel numbers of the edge detection circuit. In this paper, we proposed a electronic switch to minimize the power consumption owing to the numeric increment of the edge detection circuit to realize a vision chip for edge detection with high resolution. We also applied a method by which photodetector and edge detection circuit are separated to implement a vision chip with a higher resolution. The photodetector circuit with $128{\times}128$ pixels uses a common edge detection circuit with $1{\times}128$ pixels so that resolution was improved at the same chip area. The chip size is $4mm{\times}4mm$ and the power consumption was confirmed to be about 20mW using SPICE.