• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.4
• /
• pp.671-678
• /
• 2017

Recent advances in Internet of Things (IoT) encourage us to use IoT devices in daily living areas. However, as IoT devices are being ubiquitously used, concerns onsecurity and privacy of IoT devices are getting grown. Key management is an important and fundamental task to provide security services. For better security, we should restrict reusing a same key in sequential authentication sessions, but it is difficult to manually update and memorize keys. In this paper, we propose a hardware security module(HSM) for automated key management in IoT devices. Our HSM is attached to an IoT device and communicates with the device. It provides an automated, secure key update process without any user intervention. The secure keys provided by our HSM can be used in the user and device authentications for any internet services.

• Journal of IKEEE
• /
• v.23 no.4
• /
• pp.1321-1327
• /
• 2019

This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.4 s.310
• /
• pp.73-79
• /
• 2006

Due to the powerful correcting performance, turbo codes have been adopted in many communication standards such as W-CDMA(Wideband Code Division Multiple Access), CDMA2000, etc., and implemented by hardware in many kind of fields. Although several hardware structures and improved algorithm have been proposed, these problems such as hardware area, operating speed and power consumption are still a major issue to be solved in practical implementations. In this paper, we designed the turbo-code decoder using MAX -SCALE operation derived from the posterior probability optimization. The proposed circuit has been measured their performance on Matlab and MaxPlusII and implemented on the FPGA As a result, when implementing the proposed algorithm on the FPGA, this circuit only occupies 616 logic elements. And comparing the performance with the MAP(Maxirnum a Posteriori) decoding algorithm, the operating speed was increased by about 40%(56.48MHz) and BER(Bit Error Rate) was increased by 6.12.

• The Journal of the Acoustical Society of Korea
• /
• v.13 no.2E
• /
• pp.58-67
• /
• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.2
• /
• pp.57-64
• /
• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.351-358
• /
• 2016

This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.3
• /
• pp.30-36
• /
• 2008

The multimedia that is characterized by multi-media, multi-features, multi-representations, huge volume, and varieties, is rapidly spreading out due to the increasing of application domains. Thus, it is urgently needed to develop a multimedia information system that can retrieve the needed information rapidly and accurately from the huge amount of multimedia data. For the content-based retrieval of moving picture, picture information is generally used. It is generally used when video is segmented. Through that, it can be a structural video browsing. The tasking that divides video to shot is called video segmentation, and detecting the cut for video segmentation is called cut detection. The goal of this paper is to divide moving picture using HMMD(Hue-Mar-Min-Diff) color model and edge histogram descriptor among the MPEG-7 visual descriptors. HMMD color model is more familiar to human's perception than the other color spaces. Finally, the proposed retrieval system is implemented as hardware.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.11
• /
• pp.1707-1712
• /
• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.7
• /
• pp.1608-1616
• /
• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.6
• /
• pp.1343-1352
• /
• 2018

This paper is designed for hardware to be applied to JPEG2000 standard in the fields of digital photography, remote sensing, aerial remote telemetry, medical imaging, high resolution, and high compression telemetry applications. The software implementation of the JPEG2000 standard for image compression has disadvantages that the processing speed is very slow compared to the conventional JPEG, also the degradation occurs when the DWT level of the JPEG2000 standard is improved. In order to solve this problem, we designed and applied JPEG2000 compression/decompressor. In this paper, the hardware of the JPEG 2000 compression/storage device shows optimal compression speed, faster processing speed, and the image quality for still images by changing the optimal DWT level.