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A Hardware Implementation of Pyramidal KLT Feature Tracker  

Kim, Hyun-Jin (Dept. of Electronic Engineering, Sogang Univ.)
Kim, Gyeong-Hwan (Dept. of Electronic Engineering, Sogang Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.46, no.2, 2009 , pp. 57-64 More about this Journal
Abstract
This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.
Keywords
Feature tracking; KLT tracker; FPGA implementation; Feature point extraction;
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