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An Implementation of Turbo -Code Decoder using Posteriori Probability Optimization  

Noh Jin-Soo (Dept. of Electronic Engineering, Chosun University)
Rhee Kang-Hyeon (Dept. of Electronic Engineering, Chosun University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.43, no.4, 2006 , pp. 73-79 More about this Journal
Abstract
Due to the powerful correcting performance, turbo codes have been adopted in many communication standards such as W-CDMA(Wideband Code Division Multiple Access), CDMA2000, etc., and implemented by hardware in many kind of fields. Although several hardware structures and improved algorithm have been proposed, these problems such as hardware area, operating speed and power consumption are still a major issue to be solved in practical implementations. In this paper, we designed the turbo-code decoder using MAX -SCALE operation derived from the posterior probability optimization. The proposed circuit has been measured their performance on Matlab and MaxPlusII and implemented on the FPGA As a result, when implementing the proposed algorithm on the FPGA, this circuit only occupies 616 logic elements. And comparing the performance with the MAP(Maxirnum a Posteriori) decoding algorithm, the operating speed was increased by about 40%(56.48MHz) and BER(Bit Error Rate) was increased by 6.12.
Keywords
Turbo code; MAP; MAX-SCALE; Posterior Probability; FPGA;
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Times Cited By KSCI : 1  (Citation Analysis)
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