• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5425-5448
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• 2018

Wireless sensor network has been widely used in Internet of Things (IoT) applications to support large and dense networks. As sensor nodes are usually tiny and provided with limited hardware resources, the existing multiple access methods, which involve high computational complexity to preserve the protocol performance, is not available under such a scenario. In this paper, we propose an intelligent Medium Access Control (MAC) protocol selection scheme based on machine learning in wireless sensor networks. We jointly consider the impact of inherent behavior and external environments to deal with the application limitation problem of the single type MAC protocol. This scheme can benefit from the combination of the competitive protocols and non-competitive protocols, and help the network nodes to select the MAC protocol that best suits the current network condition. Extensive simulation results validate our work, and it also proven that the accuracy of the proposed MAC protocol selection strategy is higher than the existing work.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1714-1719
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• 2003

Antilock Brake System (ABS) is indispensable safety equipment for vehicles today. In order to develop new ABS ECU suitable for pneumatic brake system of a bus, a Hardware In-the-Loop Simulation (HILS) System was developed. In this HILS, the pneumatic brake system of a bus and antilock brake component were used as hardware. For the computer simulation, the 14-Degree of Freedom (DOF) bus dynamic model was constructed using the Matlab/Simulink software package. This model was compiled and downloaded in the simulation board, where the Power PC processor was used for real-time simulation. Additional commercial package, the ControlDesk was used to monitor the dynamic simulation results and physical signal values. This paper will focus on the procedure and results of evaluating the ECU in the HILS simulation. Two representative cases, wet basalt road and $split-{\mu}$ road, were used to simulate real road conditions. At each simulated road, the vehicle was driven and stopped under the help of the developed ECU. In each simulation, the dynamical behavior of the vehicle was monitored. After enough tests in the laboratory using HILS, the parameter-tuned ECU was equipped in a real bus, which was driven and stopped in the real test field in Korea. And finally, the experiment results of ABS equipped vehicle's dynamic behavior both in HILS test and in test fields were compared.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.364-370
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• 2011

The Hilbert transform performs a role to transform band pass signals into low pass signals in wireless communication systems. The operation of Hilbert transform is based on a convolution process which is required adding and multiplying calculations. When the Hilbert transform is designed and hardware-implemented at gate level, the adding and multiplying operation requires a high power consumption and a occupation of wide area on a chip. So the results of adding and multiplying operation cause to degrade the performance of implemented system. In this paper, the new Hilbert transformer is proposed, which has a low hardware complexity by application of MAG(Minimum Adder Graph) algorithm. The proposed Hilbert transformer was simulated in ISE environment of Xilinx and showed the reduction of hardware complexity comparing with the number of gate in the conventional Hilbert transformer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.123-128
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• 2017

In this paper, we have proposed and implemented a smart sensor network system based on the Arduino open source hardware. The proposed smart sensor network system is composed of kinds of sensors and open-source hardware based, Arduino, etc. that can handle the measured sensor values. Also the communication modules that can be used to transmit the measured sensor values from the sensor control unit are configured. In the control unit the sensor data such as temperature, humidity, light intensity can be transmit to the main program and the main program will save the data in the DB or transmitting the value of the particular control signal to the control device or the actuator. The user can also check the information in the system using the measured values from the smart sensor networks through the web, or to remotely control a variety of actuators. And it is possible to manage a smart autonomous control over whether and how the proposed system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.13-20
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• 2008

Reliability is absolutely necessary in most recent mission critical systems which usually utilize the Ethernet based computer networks. A typical way to increase system reliability is to equip the fault tolerant Ethernet. In this paper we try to formulate the fault tolerant dual Ethernet concept and presents a comparison of its implementation approaches. Two types of dual Ethernet configuration are analyzed; the divided and the connected. Then the characteristics of three current implementation approaches which are the hardware based, the software based, and the recently proposed hybrid approach are compared. The results show that the hardware based or the hybrid approaches can be a better solution for the real time mission critical systems. Also for the systems which require the use of Commercial-Off-The-Shelf (COTS) hardware for fault tolerant Ethernet the possible choice is the software based or the hybrid approach.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.1
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• pp.3-16
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• 2010

Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of ${\eta}_T$ pairing which is one of various pairing scheme. we suggest efficient hardware architecture of ${\eta}_T$ pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over GF($2^{239}$). Our implementation gives 15% better result than others in Area Time Product.

• Journal of Engineering Education Research
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• v.6 no.2
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• pp.22-29
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• 2003

The ultimate goal of a hardware design course is to equip the students with the system design ability. However, the majority of the current structures of the design courses are focused on the understanding of the operational principles of each device which is used later as a building block for the design of a system. The shortcomings of this approach are, first, that it is very hard to keep the students motivated to the end of the course where system design concepts are dealt, and, second, the students do not have enough experience of the system design which is usually required in the field. As an alternative to solve these problems, it is necessary to reverse the order of contents of the course. Namely we introduce the high level of the abstract concept of the system design in the very beginning of the course and later by lowering the level of abstraction to the operational principle of the internal devices. In this paper, we propose a new top-down methodology for the introductory hardware design course of logic design, where the design expression and verification in the system-level are introduced first and then detail knowledge on each device is introduced later. Also, we report a case result from a student's working group as part of an extracurricular education in order to verify the validity of our proposed approach

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).