Journal of the Korea Institute of Information Security & Cryptology (정보보호학회논문지)

Korea Institute of Information Security and Cryptology (한국정보보호학회)
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Efficient Hardware Implementation of ${\eta}_T$ Pairing Based Cryptography

${\eta}_T$ Pairing 알고리즘의 효율적인 하드웨어 구현

  • Lee, Dong-Geoon (Department of Computer Science Engineering, Pusan National University) ;
  • Lee, Chul-Hee (Department of Computer Science Engineering, Pusan National University) ;
  • Choi, Doo-Ho (Electronic and Telecommunications Research Institute(ETRI)) ;
  • Kim, Chul-Su (Chang Shin Infotel Co., LTD) ;
  • Choi, Eun-Young (Korea Internet & Security Agency) ;
  • Kim, Ho-Won (Department of Computer Science Engineering, Pusan National University)
  • 이동건 (부산대학교 컴퓨터공학과) ;
  • 이철희 (부산대학교 컴퓨터공학과) ;
  • 최두호 (한국전자통신연구원 정보보호연구본부) ;
  • 김철수 (창신정보통신(주) 기업부설연구소) ;
  • 최은영 (한국인터넷진흥원) ;
  • 김호원 (부산대학교 컴퓨터공학과)
  • Published : 2010.02.28
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Abstract

Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of ${\eta}_T$ pairing which is one of various pairing scheme. we suggest efficient hardware architecture of ${\eta}_T$ pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over GF($2^{239}$). Our implementation gives 15% better result than others in Area Time Product.

최근 무선 센서 네트워크 보안 분야에서는 키 교환을 위한 부가적인 통신이 필요 없이 통신 엔터티 상호간에 암호화를 수행할 수 있는 페어링 암호가 주목받고 있다. 본 논문에서는 이러한 페어링 암호의 한 종류인 ${\eta}_T$ 페어링에 대한 효율적인 하드웨어 구현을 제시한다. 이를 위해 병렬 처리 및 레지스터/자원의 최적화에 기반한 ${\eta}_T$ 페어링 알고리즘에 대한 효율적인 하드웨어 구조를 제안하며, 제안한 구조를 GF($2^{239}$) 상에서 FPGA로 구현한 결과를 나타낸다. 제안한 구조는 기존의 구현 결과에 비해 Area Time Product에 있어 15% 나은 결과를 가진다.

Keywords

References

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