• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1079-1083
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• 2002

We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMSIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flvback method, we can isolate the 1ow voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STD). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.36-46
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• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.469-472
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• 2002

We made ESD tester to measure ESD threshold voltage of semiconductor devices. The HBM ESD test is the most popular method to measure the ESD threshold voltage of MMIC. We use flyback method which is one of the DC-DC converter to get high ESD voltage. With flyback method, we can isolate the low voltage part from the high voltage part of HBM ESD tester. We use an air gap of the relay which is used for switch to satisfy the rise time of ESD standard(MIL-STll-883D). As a result, with the flyback method and the air gap of relay, we can make ESD tester whose parasitic components are minimized.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.288-292
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• 2002

We propose the new type of on-chip ESD protection method for RF applications. By using the properties of RF circuits, we can use the short-circuited stub as ESD protection device in front of the DC blocking capacitor Specially, we can use short-circuited stub as the portion of the matching circuit so to reduce the and various parameters of the transmission line. This new type ESD protection method is very different from the conventional ESD protection method. With the new type ESD protection method, we remove the parasitic capacitance of ESD protection device which degrade the performance of core circuit.

• Clinical Endoscopy
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• v.56 no.6
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• pp.778-789
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• 2023

Background/Aims: Hybrid endoscopic submucosal dissection (ESD), in which an incision is made around a lesion and snaring is performed after submucosal dissection, has some advantages in colorectal surgery, including shorter procedure time and preventing perforation. However, its value for rescue resection in difficult colorectal ESD cases remains unclear. This study evaluated the utility of rescue hybrid ESD (RH-ESD). Methods: We divided 364 colorectal ESD procedures into the conventional ESD group (C-ESD, n=260), scheduled hybrid ESD group (SH-ESD, n=69), and RH-ESD group (n=35) and compared their clinical outcomes. Results: Resection time was significantly shorter in the following order: RH-ESD (149 [90-197] minutes) >C-ESD (90 [60-140] minutes) >SH-ESD (52 [29-80] minutes). The en bloc resection rate increased significantly in the following order: RH-ESD (48.6%), SH-ESD (78.3%), and C-ESD (97.7%). An analysis of factors related to piecemeal resection of RH-ESD revealed that the submucosal dissection rate was significantly lower in the piecemeal resection group (25% [20%-30%]) than in the en bloc resection group (40% [20%-60%]). Conclusions: RH-ESD was ineffective in terms of curative resection because of the low en bloc resection rate, but was useful for avoiding surgery.

• Journal of IKEEE
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• v.28 no.2
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• pp.204-208
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• 2024

In this paper, we propose an ESD protection circuit that applies structural changes to LVTSCR, a general low-voltage ESD protection circuit, to improve the current driving capability (IEC-ESD) characteristics of the ESD protection circuit. Power consumption was minimized by separating the area where the electric field and ESD current path are formed in the LVTSCR structure, and the electrical characteristics were analyzed and current driving characteristics were improved. Structural problems resulting from deterioration of system level characteristics were analyzed through simulation, and the characteristics were verified by reflecting this. The electrical characteristics of the proposed ESD protection circuit were verified using a TCAD simulator and analyzed through HBM modeling and system level modeling. In addition, silicon production and HBM 10kV characteristics were verified through DB-Hitek 0.18um BCD process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• Journal of Fisheries and Marine Sciences Education
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• v.27 no.6
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• pp.1797-1811
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• 2015

This study is to analyze the local community-connected Education for Sustainable Development (ESD) programs that 17 clubs' students and teachers developed and implemented for their ESD club activities in elementary and middle schools. For this study, ESD elements in the programs are analyzed and the way of connection between the local communities' organizations and the ESD clubs is inquired. The process of ESD club activities is also analyzed and the change of students after the local community-connected ESD club activities is examined. Finally, the way of dissemination to local communities after ESD club activities is inquired. This study is to contribute to the practice of the local community-connected ESD in a way that develops core competencies in elementary and middle school students that will allow them to build a sustainable future in local communities.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1289-1294
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• 2008

Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.