• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2275-2276
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• 2008

Currently the quarter prediction giga it is used SE3208 from EISC ISA [1]] where it does in base. But the prediction which is perfect is difficult improved Pipeline structures and PC the structure which is not Delay to add it decided. Even PC and IF/ID blocks, the area and expense were added, but Bubble without it will be able to control Conditional Branch doors and the possibility of decreasing a help in processor performance improvements.

• The Journal of Korean Association of Computer Education
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• v.18 no.2
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• pp.71-81
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• 2015

In the EISC processor, the Instruction Queue (IQ) supporting LERI folding and loop buffering occupies roughly 20% of real estate, and its efficient utilization is a key for performance. This paper presents an architectural enhancement for the IQ utilization with return address stack (RAS) in the EISC processor. The proposed architecture eliminates the RAS corruption from the wrong-path, taking advantage of shallow pipeline. In experiments, a 4-entry RAS reduces the number of IQ flushes by up to 58.90% over baseline, and an 8-entry RAS by up to 61.28%. The experiments show up to 3.47% performance improvement with 8-entry RAS and up to 3.15% performance improvement with 4-entry RAS.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.153-158
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• 2010

Most of software developers use the GNU Debugger (GDB) in order to debug code execution. The GDB supports a remote debugging environment through serial communication. However, in embedded systems, the speed is limited in the serial communication. Due to this reason, the serial communication is rarely used for the debugging purpose. To solve this problem, many embedded systems adapt the JTAG and the USB interface. This paper proposes debugging environment via USB-JTAG interface to debug the EISC processor, and introduces how the USB interface works on the GDB and how the JTAG module handles debugging packets.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.47-48
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• 2009

많은 개발자들은 프로세서 디버깅을 위해 GDB를 사용한다. 임베디드 시스템에서 GDB의 원격 디버깅은 시리얼 통신을 사용한다. 그러나, 시리얼 통신은 속도에 제한이 있으며, 시리얼 포트 마저 점차 사라져 가는 추세이다. 이를 극복하기 위해 많은 임베디드 시스템이 JTAG 인터페이스를 탑재하고 있으며, USB 인터페이스를 사용하여 통신을 한다. 이 논문에서는 EISC 아키텍처 기반의 임베디드 시스템을 디버깅하기 위한 USB-JTAG 인터페이스 개발 방법을 제안하고, GDB 환경에서의 USB 인터페이스 구축 방법과 디버깅 패킷을 분석하기 위한 JTAG 모듈의 개발 방법을 소개한다.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.2
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• pp.96-102
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• 2014

The embedded processor market has grown rapidly and consistently with the appearance of mobile devices. In an embedded system, the power consumption and execution time are important factors affecting the performance. The system performance is determined by both hardware and software. Although the hardware architecture is high-end, the software runs slowly due to the low quality of codes. This study compared the performance of two major compilers, LLVM and GCC on a32-bit EISC embedded processor. The dynamic instructions and static code sizes were evaluated from these compilers with the EEMBC benchmarks.LLVM generally performed better in the ALU intensive benchmarks, whereas GCC produced a better register allocation and jump optimization. The dynamic instruction count and static code of GCCwere on average 8% and 7% lower than those of LLVM, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.316-318
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• 2006

루프버퍼는 루프의 부하를 줄이기 위해 일반적으로 사용되고 있는 구조이다. 본 논문은 EISC 내장형 프로세서의 에너지 소모를 줄이기 위하여 변형된 루프버퍼를 제안한다. 제안하는 루프버퍼는 EISC 프로세서가 갖는 특수 명령어의 수행 횟수를 감소시켜, 주요 에너지 소모원인 메모리 접근을 추가로 감소시킨다. 시뮬레이션 결과, 제안하는 루프버퍼는 설계한 프로세서의 수행시간을 $5%{\sim}13.6%$ 감소시키며, 메모리 접근횟수를 $14.9{\sim}37.8%$ 감소시키는 것을 관찰하였다. 변형된 루프버퍼는 $0.18{\mu}m$, 1.8V 공정 표준 셀 라이브러리를 사용하여 악 2792 개의 등가 게이트에 해당하는 면적에서 구현할 수 있다.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.