[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/IEIESPC.2015.4.5.366

Design of a G-Share Branch Predictor for EISC Processor

Kim, InSik (Department of Automotive Convergence, Korea University)
Jun, JaeYung (Department of Electrical and Computer Engineering, Korea University)
Na, Yeoul (Department of Electrical and Computer Engineering, Korea University)
Kim, Seon Wook (Department of Electrical and Computer Engineering, Korea University)

Publication Information

IEIE Transactions on Smart Processing and Computing / v.4, no.5, 2015 , pp. 366-370 More about this Journal

Abstract

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

Keywords

Microarchitecture; Branch predictor; Digital logic circuits;

Citations & Related Records

Reference

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