• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.2
• /
• pp.302-312
• /
• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.249-250
• /
• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Proceedings of the Korean Information Science Society Conference
• /
• 2010.06b
• /
• pp.112-115
• /
• 2010

차량전장용 소프트웨어에 대한 합리적인 설계 및 테스트가 중요해졌다. 차량전장용 소프트웨어의 신뢰성을 검증하기 위해 AUTOSAR Conformance Test 표준이 마련되었는데, AUTOSAR Conformance Test 표준에는 테스트 대상, 테스트 커버리지, 테스트 요구조건 & 케이스 정의 및 테스트 아키텍처 환경에 대한 정의방법을 기술하고 있다. 본 논문에서는 차량전장용 소프트웨어의 안정성을 테스트하기 위해 소프트웨어가 저장되는 EEPROM 메모리에 대한 시뮬레이션 테스트를 수행하였으며, AUTOSAR 표준에 맞게 제작된 EEPROM Abstraction 시뮬레이션 모듈을 이용하였다. 또한 EEPROM Abstraction 시뮬레이션 모듈 위에서 AUTOSAR Conformance Test 표준에 정의된 적합성 테스트를 수행하기 위한 테스트 어댑터와 타겟 어댑터의 기능을 기술하고, EEPROM Abstraction 시뮬레이션 모듈에서 리얼타임 요소를 만족하기 위해 필요한 개선 사항을 제안하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.3
• /
• pp.486-495
• /
• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 2006.06a
• /
• pp.529-532
• /
• 2006

스마트카드의 EEPROM은 갱신, 삭제가 가능한 프로그램 및 데이터가 저장되는 저장장치로서, 호스트 환경(PC환경)의 하드디스크와 같은 역할을 한다. 스마트카드의 EEPROM에 데이터를 저장하는 과정은 먼저 EEPROM의 데이터를 지우고, 새로운 데이터를 쓰는 두 단계로 이루어져 있기 때문에 중요 데이터에 대한 무결성을 보장하기 위해서 atomic operation은 하드웨어로서 지원하지 못할 경우 반드시 소프트웨어적으로 지원되어져야한다. 스마트카드 운영체제의 Atomic operation이 수행되는 과정에서 EEPROM의 버퍼 구조의 설계는 스마트카드의 수명과 밀접한 관계가 있으며, 파일에 접근하여 데이터를 처리하는 시간에 대하여 의존도가 매우 높다. 이에 본 논문에서는 스마트카드의 atomic operation 메커니즘에 대하여 알아보고, atomic operations 메커니즘을 지원하는 EEPROM의 Capabilities 증가 구조 제안과 효율적으로 파일의 접근 속도를 최소화하는 구조를 제안 한다.

• Electrical & Electronic Materials
• /
• v.7 no.2
• /
• pp.123-129
• /
• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.2
• /
• pp.113-117
• /
• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2002.11b
• /
• pp.987-990
• /
• 2002

스마트카드의 비휘발성 메모리로서 많이 쓰이는 EEPROM 은 사용에 주의해야 할 특성이 있다. 한번에 읽기, 쓰기에 접근할 수 있는 양의 개념으로 페이지가 쓰이면서, 특히 쓰기에서 여러 페이지에 걸친 부분에 접근할 매는 여지없이 기다려야 하는 블록시간이 존재한다. 이 블록 시간으로 하여 EEPROM 의 메모리 관리는 이음새 없는 하나의 덩어리 공간으로 다룰 때 오버로드를 포함하게 되어 특히, 사용자와 직접적인 통신인 되는 장치에 들어가는 EEPROM 일 때는 그 응답시간에 영향을 주게 되는 부분이다. 또한 쓰기에 있어 EEPROM 의 각 부분은 회수 제한이 있기 때문에 이를 고려해서 본 논의는 비휘발성 메모리로서 EEPROM을 대상으로 그 효율적인 관리 기법을 제안한다.

• Aerospace Engineering and Technology
• /
• v.5 no.2
• /
• pp.188-194
• /
• 2006

This paper deals with the development of Engineering Model for the TCU( Thruster Control Unit) and simulation system of the reaction control system using cold gas. TCU communicates with TLM(Telemetry) and ground control console so that it transmits monitoring data of pressures and temperatures for reaction control system. The cpu/communication board performs MIL-STD-1553B communication, RS-422 communication, data input/output processing and program loading to EEPROM. We applied Intel 80386DX Microprocessor, 256Kbytes EEPROM and 256Kbytes SRAM for program storage and execution. Also, we developed the direct access interface circuit to EEPROM and simulation system for TCU.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.4
• /
• pp.913-920
• /
• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.