• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.52-59
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• 2009

In modern radars, dynamic range requirements far severed due to high CNR(Clutter-to-Noise Ratio) environment operation scenario. ADC spurious signal restricted the required dynamic range. In this paper, receiver gain of active phased array radar dependent on ADC nonlinear characteristic was analyzed. Within limited scope of ADC SFDR which blocks required system dynamic range, ADC dynamic range reaches trade-off with ADC SNR loss. Comparing antenna stage output noise voltage to that of ADC input, receiver gain was mathematically analyzed. Finally the whole contents were explained from the application example.

• ETRI Journal
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• v.39 no.2
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• pp.292-299
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• 2017

We propose pulse-mode dynamic $R_on$ measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero-voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic $R_on$ of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from $ 0.1{\mu}s$ to 100 ms, the dynamic $R_on$ decreased from $160\Omega$ to $2\Omega$. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1389-1399
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• 2015

This research suggests maximum power point tracking (MPPT) for the solar photovoltaic (PV) power scheme using a new constant voltage (CV) fractional order incremental conductance (FOINC) algorithm. The PV panel has low transformation efficiency and power output of PV panel depends on the change in weather conditions. Possible extracting power can be raised to a battery load utilizing a MPPT algorithm. Among all the MPPT strategies, the incremental conductance (INC) algorithm is mostly employed due to easy implementation, less fluctuations and faster tracking, which is not only has the merits of INC, fractional order can deliver a dynamic mathematical modelling to define non-linear physiognomies. CV-FOINC variation as dynamic variable is exploited to regulate the PV power toward the peak operating point. For a lesser scale photovoltaic conversion scheme, the suggested technique is validated by simulation with dissimilar operating conditions. Contributions are made in numerous aspects of the entire system, including new control algorithm design, system simulation, converter design, programming into simulation environment and experimental setup. The results confirm that the small tracking period and practicality in tracking of photovoltaic array.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Journal of Magnetics
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• v.19 no.1
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• pp.90-100
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• 2014

Position estimation that uses only active phase voltage and current is presented, to perform high accuracy position sensorless control of a SRM drive. By extracting the amplitude of the first switching harmonic terms of phase voltage and current for a PWM period through Fast Fourier Transform (FFT), the flux-linkage and position are estimated without external hardware circuitry, such as a modulator and demodulator, which result in increased cost, as well as large position estimation error, produced when the motional back EMF is ignored near zero speed. A two-phase SRM drive system, consisting of an asymmetrical converter and a conventional closed-loop PI current controller, is utilized to validate the performance of the proposed position estimation scheme in comprehensive operating conditions. It is shown that the estimated values very closely track the actual values, in dynamic simulations and experiments.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1034-1037
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• 2002

A switched-capacitor(SC) type DC-DC converter having capability of integrated circuit fabrication have been marked for the application of mobile equipments. Especially, a ring type SC power supply is featured by the flexible and dynamic voltage conversion ratio change. In this paper, an improvement of the gate driving techniques is proposed for high power efficiency and less area occupation on the chip. Furthermore, its power-saving operation in the stand-by state is proposed. The three-capacitors ring type power supply is really designed and discussed. As results, the simulation results shows the high efficiency of 92.1%, and the higher output put voltage of 10.5 V compared with conventional one of 8.6 V.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1403-1412
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• 2019

A coupled inductor-dual boost-inverter (CIDBI) with a differential structure has been presented for application to a micro-inverter photovoltaic module system due to its turn ratio of a high-voltage level. However, it is difficult to design a CIDBI converter with a conventional PI regulator to be stable and achieve good dynamic performance, given the fact that it is a high order system. In view of this situation, a sliding mode control (SMC) strategy is introduced in this paper, and two different sliding mode controllers (SMCs) are proposed and adopted in the left and right side of two Boost sub-circuits to implement the corresponding regulation of the voltage and current. The schemes of the SMCs have been elaborated in this paper including the establishment of a system variable structure model, selection of the sliding surface, determination of the control law, and presentation of the reaching conditions and sliding domain. Finally, the mathematic analysis and the proposed SMC are verified by experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.3
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• pp.17-23
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• 2020

This paper proposes a simulation model using an equivalent circuit for the development of an MMC system. The MMC has been chosen as the most suitable topology for high voltage power transmission, such as a voltage-type HVDC, and it has dozens to hundreds of sub-modules in the form of a half-bridge or full-bridge connected in series. A simulation study is essential for the development of an MMC algorithm. On the other hand, it is virtually impossible to construct and implement MMC simulation models, including hundreds or thousands of switching devices. Therefore, this paper presents an MMC equivalent model, which is easily expandable and implemented by modeling the dynamic characteristics. The voltage and current equation of the equivalent circuit was calculated using the direction of the arm current and switching signal. The model was implemented on Matlab/Simulink. In this paper, to show the validity of the model developed using Matlab/Simulink, the simulation results of a five-level MMC using the real switching element and the proposed equivalent model are shown. The validity of the proposed model was verified by showing that the current and voltage waveform in the two models match each other.