• Journal of Power Electronics
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• v.7 no.2
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• pp.118-123
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• 2007

This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.525-526
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• 2009

Due to the limitation of battery life time, energy is one of the most crucial issues for wireless sensor networks. Thus this paper proposes an energy efficient duty cycle scheme to conserve energy mostly. To handle the large varieties of data (i.e., both low and high traffic load) the proposed duty cycle scheme ensures a fair access period (FAP) and a prioritized access period (PAP). The idea presented in this paper able to reduce the collision probability and energy consumption. Finally simulation outputs have demonstrated the effectiveness of the proposed duty cycle task and showed a noticeable performance in terms of energy usage.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.527-528
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• 2009

Presuming energy as a crucial resource, several duty cycle based MAC protocol have been proposed for wireless sensor network. However, these protocols have long latency problem for paying more attention on energy efficiency. In this paper, we propose Data Predicted Wakeup Based Duty Cycle MAC (DPW-MAC) for Wireless Sensor Networks for delay sensitive periodic applications in which timely delivery of data is a major concern with the maintenance of duty cycle.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.3
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• pp.154-161
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• 2005

The durability of a vehicle is a very important performance which can be evaluated from endurance test. This study developed a procedure for determination of a duty cycle theoretically. Vehicle load data is classified and rearranged using standard test road profile. A load pattern and a duty cycles are extracted from classified vehicle data using genetic algorithm. A duty cycle could be utilized in dynamo test to meet required test mileage. The derived duty cycles have been verified by fatigue test through the dynamometer test.

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1320-1330
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• 2017

Wireless sensor networks for forest monitoring are typically deployed in fields in which manual intervention cannot be easily accessed. An interesting approach to extending the lifetime of sensor nodes is the use of energy harvested from the environment. Design constraints are application-dependent and based on the monitored environment in which the energy harvesting takes place. To reduce energy consumption, we designed a power management scheme that combines dynamic duty cycle scheduling at the network layer to plan node duty time. The dynamic duty cycle scheduling is realized based on a tier structure in which the network is concentrically organized around the sink node. In addition, the multi-paths preserved in the tier structure can be used to deliver residual packets when a path failure occurs. Experimental results show that the proposed method has a better performance.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of Korean Society for Atmospheric Environment
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• v.26 no.4
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• pp.403-411
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• 2010

Recently, emission tests for heavy-duty vehicles have been conducted by heavy-duty engine dynamometer. But, it contains weaknesses that present inconveniences to install and uninstall engines and limitations to reflect on practical characteristics for vehicle driving. On the other hand, chassis dynamometer test is able to differentiate characteristics of real driving patterns due to the reason that vehicles can be examined by utilizing chassis dynamometer. This study aimed at comparing the characteristic of emitting regulatory substances of urban buses on Heavy-duty chassis dynamometer. The characteristic was analyzed based on vehicle speed by using both domestic and overseas developed heavy-duty vehicle test modes. As a result, this work attempted to investigate possibilities to take advantage of Heavy-duty vehicle test modes as a method to manage emissions from heavy-duty vehicles.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.129-131
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• 2006

This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.