• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.69-76
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• 2000

A dual-modulus prescaler divides the input signal by one of the moduli according to the control signal. In this paper, a new fast dual-modulus prescaler is proposed. The proposed prescaler has a ratioed-NOR structure different from a conventional ratioed-NAND structure. The proposed one can operate at a higher speed by using parallely connected NMOSs instead of using series-connected ones. HSPICE simulation results using HYUNDAI 0.65(m 2-poly 2-metal CMOS process parameters show that the maximum operating frequency of the proposed dual-modulus prescaler is 2.8㎓ with power consumption of 40.7㎽ at 5V supply voltage at $25^{\circ}C$. The proposed dual-modulus prescaler can be utilized for the frequency-synthesis in cellular radio front-ends.

• 한국ITS학회:학술대회논문집
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• 2005.11a
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• pp.249-252
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• 2005

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1582-1589
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• 2000

A dynamic D-flipflop is proposed aiming at low power and high frequency(GHz) operations. The proposed D-flipflop uses a smaller number of pmos transistors that it operates high speed in same dimensions. Also, it consumes lower power than conventional approaches by a shared nmos with clock input. In order to compare the performance of the proposed D-flipflop, we perform simulation estimating power consumption and maximum operating frequency of each same dimension D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop is evaluated via the same method. The simulation results show that the proposed D-fliplflop has good performance than conventional circuits.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.271-274
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• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.179-182
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• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.43-53
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• 2002

In this paper, a new dynamic D-flip-flop which does not suffer from charge sharing and glitch problems is proposed. And a dual-modulus divide-by-128/129 prescaler has been designed with the proposed D-flip-flops using a 0.6$0.6{\mu}m$ CMOS technology. Eleven-transistor architecture enables it to operate at the higher frequency range and the transistor merging technique contributes to the reduction of power consumption. At 5V supply voltage, the simulated maximum operating frequency and the current consumption of the divide-by-128/129 prescaler are 1.97GHz and 7.453mA, respectively.