Browse > Article

Design of a CMOS IF PLL Frequency Synthesizer  

김유환 (텔슨전자(주))
권덕기 (인천대학교 전자공학과)
문요섭 (인천대학교 전자공학과)
박종태 (인천대학교 전자공학과)
유종근 (인천대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.8, 2003 , pp. 598-609 More about this Journal
Abstract
This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.
Keywords
IF PLL; VCO; CMOS; prescaler;
Citations & Related Records
연도 인용수 순위
  • Reference
1 W. S. T. Van and H. C. Luong, 'A 2-V 900MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers', IEFE J. Solid-State Circuit, vol.36, no.2, pp. 204-216, Feb. 2001   DOI   ScienceOn
2 김유환, 권덕기, 김거성, 이종렬, 박종태, 유종근, '프로그래머블 CMOS Tx IF PLL 설계,' 제3회 전자 정보통신 학술대회 논문집, pp. 349-352, 2001
3 D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, 1991
4 R E. Best, Phase-Locked Loops: Theory, Design, and Applications, 2nd-edition, McGraw Hill, 1993
5 Willian F. Egan, Frequency Synthesis by Phase lock, 2nd Edition, Wiley Interscience, 1999
6 B. Razavi, RF Microelectronics, Prentice Hall, 1998
7 Q. Huangand R. Rogenmoser, 'Speed Optimization of Edge-Triggered CMOS Circuit for Gigahertz Single-Phase Clock,' IEEE J. SolidState Circuit, vol.31, no.3, pp. 483-465 Mar. 196   DOI   ScienceOn
8 김유환, 인천대학교 대학원 전자공학과,이동통신 단말기용 CMOS IF PLL 주파수 합성기의 설계 및 구현, 석사학위논문, 인천대학교 대학원 전자공학과, Dec. 2002
9 권덕기, 김유환, 문요섭, 이종렬, 박종태, 유종근, '프로그래머블 IF PLL용 주파수 분주기 설계,' 제3회 전자 정보통신 학술대회 논문집, pp.341-344, 2001
10 김유환, 권덕기, 이종렬, 유종근, '저전력 CMOS 기준전류 발생회로,' 대한전자공학회 하계종합학술대회 논문집 II, 제24권, 제1호, pp. 89-92, 2001   과학기술학회마을
11 H. singh, et al., 'GaAs prescalers and counters for Fast-settling frequency synthesizer,' IEEE J. Solid-State Circuit, vol.25, no.2, pp. 239-245, Feb. 1990   DOI   ScienceOn
12 Y. Yamauchi, et al., 'A 15GHz monolithic two-modulus prescaler,' IEEE J. Solid -State Circuit, vol.26, no.11, pp. 1632-1636, Nov. 1991   DOI   ScienceOn
13 J. Yuan and C. Svensson, 'High-Speed CMOS Circuit Technique,' IEEE J. Solid-State Circuit, vol.24, no.2, pp. 62-70, Feb. 1989   DOI   ScienceOn
14 T. Brooks and A. L. Westwisk, 'Low-power differential CMOS bandgap reference,' ISSCC Digest of Tech. Papers, pp. 248-249, Feb. 1994   DOI
15 B. Chang, J. Park, and W. Kim, 'A 1.2GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Hip-Flops,' IEEE J. Solid-State Circuit, vol.31, no.5, pp. 749-752, May. 1996   DOI   ScienceOn
16 C. Yang et al., 'New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler,' IEEE J. Solid-State Circuit, vol.33, no.10, pp. 1568-1571, Oct. 1998   DOI   ScienceOn
17 Kerry Bernstein, et al., High Speed CMCS Design Styles, Kluwer Academic Publishers, pp. 194-196
18 김유환, 문요섭, 이종렬, 박종태, 유종근, '자동진폭조절 기능을 갖는 CMOS IF VCO 설계,' 대한전자공학회 하계종합학술대회 논문집 II, 제25권, 제1호, pp. 145-148, 2002   과학기술학회마을
19 M. A. Margarit, J. L. Tharn, R. G. Meyer, and M. J. Deen, 'A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wifeless Applications,' IEEE JSSC, vol.34, no.6, pp. 761-771, June 1999   DOI   ScienceOn
20 Data sheet, 'LMX1600: PLLatinum Low Cost Dual Frequency Synthesizer,' National Semiconductor, August 2000
21 Data sheet, 'MB15C101: IF Band PLL Frequency Synthesizer,' Fujitsu Semiconductor