• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2031-2033
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• 2005

poly-Si TFT의 kink 전류를 억제하는 L-shaped dual-gate TFT 구조를 제안하고 이를 제작하였다. 제안된 소자는 채널의 그레인 방향을 일정하게 성장시키는 SLS나 CW laser 결정화 방법을 사용한다. L자 모양의 게이트 구조를 사용하여 서고 다른 전계효과 이동도를 갖는 두 개의 sub-TFT를 구현할 수 있으며, 이러한 sub-TFT간의 특성차이가 kink 전류를 억제시킨다. 직접 제작한 L-shaped dual-gate 구조의 소자가 poly-Si TFT의 kink 전류를 억제하고, 전류포화 영역에서 전류량을 고정시킴으로써 신뢰성이 향상됨을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.135-135
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• 2009

In this work we compared the electrical characteristic of single gate and dual gate in MIC-TFT. We fabricated p-channel TFTs based on MIC structure. In mobility, dual gate ($61.35cm^2/Vsec$) got a higher value than single gate ($55.96cm^2/Vsec$). In $I_{on}/I_{off}$ dual gate ($6.94{\times}10^6$) got a higher value than single gate ($1.72{\times}10^6$) too. In $I_{off}$, dual gate got a lower value than single gate. Therefore, dual gate is good and less power consumption than single gate.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.342-344
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• 2005

We have simulated a symmetric dual-gate TFT which has triple floating n+ channel to improve the on-current of the dual-gate TFT. We achieved a low hole concentration at the source and channel junction causes the improvement the potential barrier so that we observed the reduction of the kink-effect. In this paper, we observed the reduction of the kink-effect compared with the conventional single-gate TFT and the improvement of the on-current compared with the conventional dual-gate TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• Transactions on Electrical and Electronic Materials
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• v.7 no.2
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• pp.53-57
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• 2006

In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.527-530
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• 2009

We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20 nm-thick $Al_2O_3$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at $200^{\circ}C$. Whether top or bottom gate is biased for sweep, our TFT almost symmetrically operates under a low voltage of 5 V showing a field mobility of ~0.4 $cm^2/V{\cdot}s$ along with the on/off ratio of $5{\times}10^4$. The threshold voltage of our DG TFT was systematically controlled from 0.5 to 2.0 V by varying counter gate input from +5 to -2 V.

• Journal of IKEEE
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• v.26 no.3
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• pp.500-505
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• 2022

In this study, we designed oxide thin-film transistors (TFTs) with dual gate and tri layered split channels, and investigated the structural effect of the TFTs on the electrical characteristics. The dual gates played a key role in increasing the driving current, and the channel structure of tri layers and split form contributed to the increase in the carrier mobility. The tri layered channels consisting of the a-ITGZO and two ITO layers inserted between the gate dielectric and a-ITGZO led to the increase in the on-current by using ITO layers with high conductivity, and the split channels lowered series resistance of the channels. Compared with the mobility (15 cm²/V·s) of the single gate a-ITGZO TFT, the mobility (134 cm²/V·s) of the dual gate tri-layer split channel TFT was remarkably enhanced by the structural effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• Applied Microscopy
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• v.39 no.4
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• pp.349-354
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• 2009

In this paper we have constructed three dimensional images and examined structural failure on thin film transistor (TFT) liquid crystal display (LCD) by using dual-beam focused ion beam (FIB) and IMOD software. Specimen was sectioned with dual-beam focused ion beam. Series of two dimensional images were obtained by scanning electron microscopy. Three dimensional reconstruction was constructed from them by using IMOD software. The short defect between Gate layer and Data layer was found from the result of three dimensional reconstruction. That phenomena made the function of the gate lost and data signal supplied to the electrode though the Drain continuously. That signal made continuous line defect. The result of the three dimensional reconstruction, serial section, SEM imaging by using the FIB will be the foundation of the next advanced study.