• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.223-229
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• 2017

This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.

• Applied Microscopy
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• 제39권4호
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• pp.349-354
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• 2009

TFT-LCD의 구조불량이 발생한 박막 트랜지스터에 대해서 집속이온빔 가공장치(Dual-beam FIB/SEM)를 이용하여 연속절편법(Serial sectioning)과 일련의 연속적인 2차원 주사전자현미경 이미지를 얻었고, IMOD 소프트웨어를 통해서 3차원 구조구현(3D reconstruction) 연구를 하였다. 3차원 구조구현 결과, Gate막과 Data막이 접합되어 있는 불량이 관찰되었다. 두 막이 접합되어서 ON/OFF 역할을 하는 Gate의 기능이 상실되었고, Data신호는 Drain을 통해서 투명전극에 전류를 공급하여 계속 빛나는 선 불량(line defect)이 발생한 것으로 판단된다. 이 논문의 결과인 집속이온빔 가공장치(Dual-Beam FIB/SEM)를 이용한 3차원 구조구현 연구와 연속절편법, 주사전자현미경 이미지작업, 이미지 프로세싱에 대한 결과는 향후 연구의 기초자료로 활용될 수 있을 것으로 판단된다.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.259-266
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• 2004

In this paper. a new two types of EST(Emitter Switched Thyristor) structures are proposed to improve the electrical characteristics including the current saturation capability. Besides, the two dimensional numerical simulations were carried out using MEDICI to verify the validity of the device and examine the electrical characteristics. First, a vortical trench electrode EST device is proposed to improve snap-back effect and its blocking voltage. Second, a dual trench gate EST device is proposed to obtain high voltage current saturation characteristics and high blocking voltage and to eliminate snap-back effect. The two proposed devices have superior electrical characteristics when compared to conventional devices. In the vertical trench electrode EST, the snap-back effect is considerably improved by using the vertical trench gate and cathode electrode and the blocking voltage is one times better than that of the conventional EST. And in the dual trench gate EST, the snap-back effect is completely removed by using the series turn-on and turn-off MOSFET and the blocking voltage is one times better than that of the conventional EST. Especially current saturation capability is three times better than that of the other EST.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.392-395
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• 2003

For the first time, the new dual trench gate Emitter Switched Thyristor is proposed for eliminating snap-back effect which leads to a lot of serious problems of device applications. Also, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in the proposed EST structure, allowing higher maximum controllable current densities for ESTs. Moreover, the new dual trench gate allows homogenous current distribution throughout device and preserves the unique feature of the gate controlled current saturation of the thyristor current. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $354/{\S}^2$, respectively. But the proposed EST exhibits snap-back with the anode voltage and current density 0.93V and $58A/{\S}^2$, respectively. Saturation current density of the proposed EST at anode voltage 6.11V is $3797A/{\S}^2$. The characteristics of 700V forward blocking of the proposed EST obtained from two dimensional numerical simulations (MEDICI) is described and compared with that of the conventional EST.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 합동춘계학술대회 논문집 전기물성,응용부문
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• pp.153-156
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• 2008

본 논문은 Local oscillator의 2차 harmonic 신호를 이용하고 Dual gate FET 형태를 이용한 이중대역 주파수 혼합기 설계에 대한 연구 이다. 기존의 회로 구조는 두 대역을 처리하기 위해 각각 두 개의 국부 발진기와 혼합기를 사용함으로 인하여 구조의 복잡함과 큰 전력 손실이라는 단점을 가지고 있었다. 본 연구는 하나의 주파수 혼합기로 두 개의 대역에서 동시에 적용할 수 있는 Concurrent 이중 대역 설계 연구를 하였다. ISM(Industrial Science Medical) 대역 인 912MHz, 2.45GHz의 RF 입력과 455.5MHz, 1224.5MHz의 LO 입력 신호에서 동일한 IF인 1MHz로 하향변환 했을 때 모의실험 결과 변환이득은 각각 7dB, 12dB로 이고 RF-LO 격리도는 -29dB, -24.7dB가 나왔다. 또한 두 입력 단에서의 반사손실의 -15dB 이상을 얻었다. 또한 각각의 대역에서 잡음지수는 8.5dB, 6.26dB이다.

• ETRI Journal
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• 제19권2호
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 한국항행학회논문지
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• 제9권2호
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• pp.103-109
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• 2005

본 논문에서는 이중게이트 FET 구조를 이용하여 광대역 하이브리드 믹서를 RF신호와 LO신호를 출력단과 격리하는 저역통과필터와 같이 설계하였다. 저역통과필터는 1.5-5.5GHz에서 RF와 LO신호에 대하여 40dBc의 억압특성을 나타낸다. 이중게이트 FET 믹서는 두 개의 FET를 캐스코드 구조로 연결하여 설계하였으며, 첫번째 FET는 선형영역에서 동작되고 두번째 FET는 포화영역에서 동작한다. 입력매칭은 1.5-5.5GHz에서 높은 변환이득을 갖도록 설계하였다. 설계된 믹서는 IF를 21.4MHz로 고정시키고 0dBm의 국부발진기 전력에서 1.5-5.5GHz 대역에서 7dB이상의 변환이득을 가진다.

• 전기학회논문지
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• 제60권12호
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• pp.2286-2292
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• 2011

In this paper we present the design of Low Noise Amplifier(LNA), mixer and filter for RF front-end part of partial discharge monitoring system. The monitoring system of partial discharge in high voltage power machinery is used to prevent many kinds of industrial accidents, and is usually composed of three parts - sensor, RF front-end and digital microcontroller unit. In our study, LNA, mixer and filter are key components of the RF front-end. The LNA consists of common gate and common source-cascaded structure and uses the resistive feedback for broad band matching. A coupled line structure is utilized to implement the filter, of which size is reduced by the meander structure. The mixer is designed using dual gate structure for high isolation between RF and local oscillator signal.