• 제목/요약/키워드: Dual Sampling

검색결과 102건 처리시간 0.02초

Dual Sampling-Based CMOS Active Pixel Sensor with a Novel Correlated Double Sampling Circuit

  • Jo, Sung-Hyun;Bae, Myung-Han;Jung, Joon-Taek;Choi, Pyung;Shin, Jang-Kyoo
    • 센서학회지
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    • 제21권1호
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    • pp.7-12
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    • 2012
  • In this paper, we propose a 4-transistor active pixel sensor(APS) with a novel correlated double sampling(CDS) circuit for the purpose of extending dynamic range. Dual sampling techniques can overcome low-sensitivity and temporal disparity problems at low illumination. To accomplish this, two images are obtained at the same time using different sensitivities. The novel CDS circuit proposed in this paper contains MOS switches that make it possible for the capacitance of a conventional CDS circuit to function as a charge pump, so that the proposed APS exhibits an extended dynamic range as well as reduced noise. The designed circuit was fabricated by using $0.35{\mu}m$ 2-poly 4-metal standard CMOS technology and its characteristics have been evaluated.

듀얼 레이트를 갖는 지능형 디지털 제어기 설계 (Design of Intelligent Digital Controller with Dual-Rate Sampling)

  • Kim, Do-Wan;Joo, Young-Hoon;Park, Jin-Bae
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 2004년도 춘계학술대회 학술발표 논문집 제14권 제1호
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    • pp.559-562
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    • 2004
  • In this paper, a new dual-rate digital control technique for the Takagi-Sugeno (T-S) fuzzy system is suggested. The proposed method takes account of the stabilizablity of the discrete-time T-S fuzzy system at the fast-rate sampling points. Our main idea is to utilize the lifted control input. The proposed approach is to obtain the dual-rate discrete-time T-S fuzzy system by discretizing the overall dynamics of the T-S fuzzy system with the lifted control, and then to derive the sufficient conditions for the stabilization in the sense of the Lyapunov asymptotic stability for this system.

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Primal Tree의 공간 분할 샘플링 분석 및 구현 (Analysis on Spatial Sampling and Implementation for Primal Trees)

  • 박태정
    • 디지털콘텐츠학회 논문지
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    • 제15권3호
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    • pp.347-355
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    • 2014
  • 컴퓨터 그래픽스나 기하 정보 분석 및 검색 등의 애플리케이션에서 일반적인 octree가 널리 사용된다. 그러나 거리장 등 공간에 분포하는 특정한 연속 정보를 샘플링하기 위한 목적으로 일반적인 octree를 적용할 경우 샘플링 데이터 중복과 샘플링 지점과 표현 단위의 불일치가 발생한다. 이 문제를 해결하기 위해 dual octree가 제안된 바 있다. 본 논문에서는 dual octree가 일반적인 octree의 단점은 해결했으나 무한하게 분할을 수행하더라도 특정한 연속 영역에 액세스하지 못한다는 사실을 증명하고 이러한 모든 문제들을 해결할 수 있는 대안으로 Lefebvre와 Hoppe가 제안한 primal tree를 응용할 수 있음을 제시한다. 또한 트리 구조의 병렬화에 널리 사용되는 Morton code를 응용한 3차원 primal tree 검색 알고리즘을 제안한다.

A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

  • Abbasizadeh, Hamed;Lee, Dong-Soo;Yoo, Sang-Sun;Kim, Joon-Tae;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권6호
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    • pp.760-770
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    • 2016
  • A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

Digital Control for Takagi-Sugeno Fuzzy System with Multirate Sampling

  • Kim, Do Wan;Joo, Young Hoon;Park, Jin Bae
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제4권2호
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    • pp.199-204
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    • 2004
  • In this paper, a new dual-rate digital control technique for the Takagi-Sugeno (T-S) fuzzy system is suggested. The proposed method takes account of the stabilizablity of the discrete-time T-S fuzzy system at the fast-rate sampling points. Our main idea is to utilize the lifted control input. The proposed approach is to obtain the dual-rate discrete-time T-S fuzzy system by discretizing the overall dynamics of the T-S fuzzy system with the lifted control, and then to derive the sufficient conditions for the stabilization in the sense of the Lyapunov asymptotic stability for this system. An example is provided for showing the feasibility of the proposed discretization method.

Hybrid State Space Self-Tuning Fuzzy Controller with Dual-Rate Sampling

  • Kwon, Oh-Kook;Joo, Young-Hoon;Park, Jin-Bae;L. S. Shieh
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1998년도 제13차 학술회의논문집
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    • pp.244-249
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    • 1998
  • In this paper, the hybrid state space self-tuning control technique Is studied within the framework of fuzzy systems and dual-rate sampling control theory. We show that fuzzy modeling techniques can be used to formulate chaotic dynamical systems. Then, we develop the hybrid state space self-tuning fuzzy control techniques with dual-rate sampling for digital control of chaotic systems. An equivalent fast-rate discrete-time state-space model of the continuous-time system is constructed by using fuzzy inference systems. To obtain the continuous-time optimal state feedback gains, the constructed discrete-time fuzzy system is converted into a continuous-time system. The developed optimal continuous-time control law is then convened into an equivalent slow-rate digital control law using the proposed digital redesign method. The proposed technique enables us to systematically and effective]y carry out framework for modeling and control of chaotic systems. The proposed method has been successfully applied for controlling the chaotic trajectories of Chua's circuit.

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A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology

  • Kim, Bin-Hee;Yan, Long;Yoo, Jerald;Yoo, Hoi-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권1호
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    • pp.23-32
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    • 2011
  • A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

  • Cho, Kyuik;Kim, Daeyun;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권4호
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    • pp.388-396
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    • 2012
  • In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

FRAMES AND SAMPLING THEOREMS IN MULTIWAVELET SUBSPACES

  • Liu, Zhanwei;Wu, Guochang;Yang, Xiaohui
    • Journal of applied mathematics & informatics
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    • 제28권3_4호
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    • pp.723-737
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    • 2010
  • In this paper, we investigate the sampling theorem for frame in multiwavelet subspaces. By the frame satisfying some special conditions, we obtain its dual frame with explicit expression. Then, we give an equivalent condition for the sampling theorem to hold in multiwavelet subspaces. Finally, a sufficient condition under which the sampling theorem holds is established. Some typical examples illustrate our results.

Pulse Dual Slope Modulation for VLC

  • Oh, Minseok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제8권4호
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    • pp.1276-1291
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    • 2014
  • In the field of visible light communication (VLC), light-emitting diodes (LEDs) are used for transmitting data via visible light. In this study, we analyze pulse dual slope modulation (PDSM) as a means of delivering information in VLC. PDSM involves the modulation of symmetrical slope pulses to encode binary 0s and 1s, and owing to the moderately increasing and decreasing pulse shapes that are created, this method enables more spectral efficiency than the variable pulse position modulation (VPPM) technique currently adopted in IEEE 802.15.7. In particular, PDSM allows for the avoidance of intra-frame flicker by providing idle pulses in a spectrum-efficient way. A simple detection scheme is proposed for PDSMsignals, and its bit error rate (BER) is analyzed mathematically at varying slopes to validate the process through simulation. The BER performance of PDSM detection using dual sampling is compared to the performances of PDSM and VPPM using correlation detection. It is found that, when the probability of idle pulse transmission is less than 0.08 and higher than 0, the BER of dual sampling PDSM is lower than that of PDSM using correlation detection over the entire light intensity range.