• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.105-108
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• 2005

We demonstrate an electro-optical device based on the flexoelectric effect of a short-pitched cholesteric liquid crystal. By using a dual-frequency switchable nematic, a small amount of chiral dopant and a small amount of phase-separated polymer localized on the surface, we were able to create a device that operates in amplitude (flexoelectric) and phase(dielectric) modes. At high frequency the dual frequency liquid crystal suppresses the phase mode at higher voltage, which improves the switching speed, and thereby preserving the in-plane-switching mode.

• Macromolecular Research
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• v.15 no.5
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• pp.396-402
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• 2007

The dielectric properties and various pattern-forming states of dual-frequency material in a nematic phase, as well as its mixture containing low concentrations of reactive monomers, are reported. The dielectric relaxation behaviors of nematic MLC 2048 are presented and compared to its mixture containing both mesogenic and nonmesogenic reactive monomers. The sign-inversion frequency of the dielectric anisotropy was significantly shifted on the addition of small amounts of the reactive monomers. However, all three mixtures used in this study essentially exhibited the same field-induced instabilities at different frequencies and voltage domains of the applied electric field. A broad band of modulated states were found to exist above a critical voltage and within a voltage dependent frequency band in the vicinity of the sign-inversion frequency, $f_I$, of the dielectric anisotropy. As the $f_I$ of the mixtures shifted, so did the bands of the modulated state of the different mixtures and the temperatures, which were well matched with the measured $f_I$ value.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.84-87
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• 2010

We manufacture an antifuse OTP (One-time programmable) cell for analog trimming which will be used in power management ICs. For the antifuse cell using dual program voltage of VPP (=7V) and VNN (=-5V), the thin gate oxide is broken down by applying a voltage higher than the hard break-down voltage to the terminals of the antifuse. The area of the manufactured antifuse OTP cell using $0.18{\mu}m$ BCD process is $48.01{\mu}m^2$ and is about 44.6 percent of that of an eFuse cell. The post-program resistances of the antifuse are good with the values under several kilo ohms when we measure twenty test patterns.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.2
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• pp.43-49
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• 2000

It is a complex process to analyze power system voltage stability problems with all of the dynamics of a system, because a large power network system sophisticatedly consists of generators, lines, loads and so forth. So we considered the dynamics of loads so as to analyze voltage stability method- by carrying out an analysis of steady state voltage stability and dynamic voltage stability simultaneously. To perform a steady state voltage stability program in advance makes it possible to cut down on laborious calculations so that an analysis of dynamic voltage stability becomes concise. The validity and efficiency of the method presented in this paper were verified by applying the IEEE 14 bus system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.832-836
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• 2015

In this paper, a DC-DC converter is designed for logic process MTP (multi-time programmable) memory IPs using dual program voltage, which are used for analog trimming or storing chip IDs in sensor applications. The DC-DC converter supplies VPP (=5.25V), VNN (=-5.25V), and VNNL ($=2{\cdot}VNN/5$). It uses MOS capacitors and designed with only 3,3V devices. VPP and VNN are configured in two and five stages, respectively. And their pumping currents are $9.17{\mu}A$ and $9.7{\mu}A$, respectively.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.237-240
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• 2002

In this paper, we designed and implemented the dual band antenna for IMT-2000 and 5.7㎓ WLAN(Wireless Local Area Network). The antenna was designed by using 3D simulations program, HFSS(High Frequency Structure Simulator). The electrical characteristics were measured by using HP 8720C network analyzer and measured maximum S$\sub$11/ was -25㏈, and maximum VSWR(Voltage Standing Wavc Ratio) was 1.26 for all frequency bands of interests in IMT-2000 and 5.7㎓ WLAN. Simulation results for antenna gain at 2㎓ and 5.7㎓ were 1.31㏈i and 4.1㏈i with omni directional radiation pattern. Implemented antenna is compact sized and can be produced in low cost enough for commercialization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.198-199
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• 2013

본 논문은 군용 UPS 시스템에서 Dual Active Bridge(DAB) 컨버터를 이용한 절연형 양방향 배터리 충전기를 제안한다. 일반적인 군용 UPS 시스템은 AC-DC 정류기, DC-AC 인버터, 양방향 DC-DC 컨버터, 배터리 충전기, 배터리로 구성되며, 여러 부하상태들에 대한 지속적인 전력공급을 위하여 안정적인 에너지 저장 시스템이 요구된다. 다양한 양방향 DC-DC 컨버터들 중, DAB 컨버터는 buck, boost 동작이 가능한 고효율 절연형 양방향 컨버터이다. 본 논문에서는 6kW(입력 380Vdc, 출력 32/21Vdc) DAB 컨버터에 대한 토폴로지 분석하고, 파라미터 및 제어 알고리즘 설계를 제안하고 시제품을 통해 이를 검증하였다.