• Journal of Navigation and Port Research
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• v.36 no.1
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• pp.69-74
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• 2012

Recent global supply chain, improving the efficiency of container shipping process is very important. In the overseas shipping of goods, the voyage of super containership is common to overcome amount of increasing cargo. Thus, container terminal managers make an experiment on the double cycle and dual cycle operation, which ship loading and unloading were carried out simultaneously, for maximizing the productivity of quay side. Yard Tractors(YTs) pooling methods also are introduced for increasing the efficiency of assignment of YTs. In this paper, we analyzed the efficiency of dual cycling through comparing existing pooling methods with the modified method for the dual cycling. We developed a simulation model using simulation analysis software, Arena. The result of experiment shown that the more dual cycling don't always increase the gross crane rate(GCR), which means productivity of quay cranes(QCs) per hour.

• Journal of Navigation and Port Research
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• v.33 no.8
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• pp.555-562
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• 2009

At container terminals, a major measurement of productivity can be work-efficiency in quay-side. At the apron, containers are loaded onto the ship and unloaded to apron by Q/C(Quay Crane). For improving the productivity of quay crane, the more efficient Y/T(Yard Tractor) operation method is necessary in container terminals. Between quay-side and yard area, current transferring methods is single-cycling which doesn't start loading unless it finishes unloading. Dual-cycling is a technique that can be used to improve the productivity of quay-side and utility of yard tractor by ship loading and unloading simultaneously. Using the dual-cycling at terminals only necessitates an operational change without purchasing extra equipment. Exactly, Y/T operation method has to be changed the dedicate system to pooling system. This paper presents an efficient ship loading and unloading plan in container terminals, which use the dual-cycling. We propose genetic and tabu search algorithm for this problem.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.252-257
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• 2011

A compact microstrip dual-band bandpass filter with controllable bandwidth for each passband is proposed. Each passband is independently designed using two different dual-mode resonators. The proposed dual-band bandpass filter has three transmission zeros. Two transmission zeros are generated by each dual-mode resonator. An additional transmission zero is generated by input/output port coupling. The dual-band bandpass filter application is designed for 2.4/5.7 GHz WLAN. Experimental results are presented to validate theory.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.251-258
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• 2023

In this paper, we propose DLP(Dual Linear Polarization) stack antenna for private network. The proposed antenna has general stack structure and design airgap between two substrate to obtain the maximum gain. Also, to improve cross polarization isolation, two feeding port is designed to separate for each substrate. The size of each patch antenna is 17.80 mm(W1)×16.70 mm(L1) for lower patch and 18.56 mm(W2)×18.73 mm(L2) for upper patch, which is designed on the FR-4 substrate which thickness (h) is 1.6 mm, and the dielectric constant is 4.3, and which is 40.0 mm(W)×40.0 mm(L) for total size of substrate. From the fabrication and measurement results, bandwidths of 100 MHz (4.74 to 4.84 GHz) for feeding port 1, and 150 MHz (4.67 to 4.82 GHz) for feeding port 2 are obtained on the basis of -10 dB return loss and transmission coefficient S21 is got under the -20 dB. Also, cross polarization isolation between each feeding port obtained

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.57-64
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• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.41-45
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• 2015

In this paper, the single port dual-band resonator for magnetic resonance wireless power transfer is proposed. The proposed dual-band resonator is consists of 20 turns spiral coil, a single loop, matching circuit, lumped elements, and a single port. The two sides of the matching circuit are connected to via holes. The spiral coil is operated at MF-band and single loop is operated at HF-band, respectively. We use two of the same structure resonators and simulated and the power transfer efficiency was calculated. The efficiency of simulation and measurement is above 60% at the MF and HF bands, and the distance is 100 mm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1034-1039
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• 2002

In this paper, the design of a dual-polarization rectangular microstrip patch antenna with high isolation between two feeding ports excited by using both an aperture-coupled feed (port 1) and a 3-dimensional microstrip feed (port 2) is presented. From the simulation using the commercial program IE3D, the optimum values of the antenna parameters are investigated at both two feed structures and the optimum antenna is designed and fabricated. Experimental results confirmed that an bandwidth of the antenna is about 17 % and the isolation of two ports is great than 30 dB over all frequency bands.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.185-190
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• 2006

The correct estimation of the ionospheric delays is very important for the precise kinematic positioning especially in case of the long baseline. In case of triple frequency system, the ionospheric delays can be estimated from the measurements, but, in case of dual frequency system, the situation is not so simple. The precision of those supplied by the external information source such as IONEX is not sufficient. The high frequency component is neglected, and the precision of the low frequency component is not sufficient for the long baseline positioning. On the other hand, the high frequency component can be estimated from the phase range measurements. If the low frequency components are estimated by using the external information source or pseudo range measurements, a more reasonable estimation of the ionospheric delays may be possible. It has already been discussed by the author that the estimation of the low frequency components by using the external information source is not sufficient but fairly effective. The estimation using the pseudo range measurements is discussed in the present paper. The accuracy is not sufficient at present because of the errors in the pseudo range measurements. It is clarified that the bias errors in the pseudo range measurements are responsible for the poor accuracy of the ionospheric delays. However, if the accuracy of the pseudo range measurements is improved in future, the method would become very promising.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.