• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.96-102
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• 2014

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

• Korean Journal of Child Studies
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• v.11 no.1
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• pp.45-57
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• 1990

The purpose of the present study was to investigate the age-related differences in recall and to assess effects of presentation modality, encoding condition and cue modality on recall in terms of encoding specificity principles and dual-coding theory. Eighty children in each of 3grades(first, third and fifth) were presented a 30-item set of pictures or words on cars for recall in a study-test procedure. The experiment was designed as a 3(age) x 2(presentation modality:picture or word) x 2(encoding condition:random or category) x 2(cue modality:picuture or word) factorial design. Statistical analyses were with four-way ANOVA and $Scheff\acute{e}$ test. It was concluded from these results that when the stimulus was presented by pictures, encoded by category and the cues were also presented by pictures, recall increased in all ages. These results were interpreted in terms of encoding specificity principles and dual-coding theory.

• Korean Journal of Microbiology
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• v.38 no.4
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• pp.239-239
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• 2002

• Journal of KIISE
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• v.44 no.10
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• pp.1034-1044
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• 2017

Although traversal strategies are important for the performance of model checking, many studies have ignored the impact of traversal strategies in model checking with a block-encoded abstract reachability graph. Studies have considered traversal strategies only for an abstract reachability graph without block-encoding. Block encoding plays a crucial role in the model checking performance. This paper therefore describes Dual-traversal strategy, a simple and novel technique to control traversal strategies in a block-encoded abstract reachability graph. This method uses two traversal strategies for a model checking, one for effective block-encoding, and the other for traversal in an encoded abstract reachability graph. Dual-traversal strategy is very simple and can be implemented without overhead compared to the existing single-traversal strategy. We implemented the Dual-traversal strategy in an open source model checking tool and compare the performances of different traversal strategies. The results show that the model checking performance varies from the traversal strategies for the encoded abstract reachability graph.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1443-1454
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• 2016

Balanced encoding method that implement Dual-rail logic style based on hardware technique to software is efficient countermeasure against side-channel analysis without additional memory. Since balanced encoding keep Hamming weight and/or Hamming distance of intermediate values constantly, using this method can be effective as countermeasure against side channel analysis due to elimination of intermediate values having HW and/or HD relating to secret key. However, former studies were presented for Constant XOR operation, which can only be applied to crypto algorithm that can be constructed XOR operation, such as PRINCE. Therefore, our first proposal of new Constant ADD, Shift operations can be applied to various symmetric crypto algorithms based on ARX. Moreover, we did not used look-up table to obtain efficiency in memory usage. Also, we confirmed security of proposed Constant operations with Mutual Information Analysis.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.1-5
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• 2008

Although we can make a sparse matrices for LDPC codes, the encoding complexity per a block increases quadratically by $n^2$. We propose modified PEG algorithm using PEG algorithm having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner. M-PEG construct parity check matrices. So we propose parity check matrices H form a dual-diagonal matrices that can construct a more efficient decoder using a M-PEG(modified Progressive Edge Growth).

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Journal of IKEEE
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• v.18 no.3
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• pp.328-334
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• 2014

This paper proposes an optical encryption and decryption system for OFB(Output Feedback Block) encryption algorithm. The proposed scheme uses a dual-encoding technique in order to implement optical XOR logic operation. Also, the proposed method provides more enhanced security strength than the conventional electronic OFB method due to the huge security key with 2-dimensional array. Finally, computer simulation results of encryption and decryption are shown to verify the proposed method, and hence the proposed method makes it possible to implement more effective and stronger optical block encryption system with high-speed performance and the benefits of parallelism.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.57-64
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• 2004

In this paper, we propose a RZ/HRZ mixture data transmission method for the asynchronous circuit design to reduce Power consumption. The dual-rail data with Rf decoding scheme is used to design asynchronous circuit, and it is easy to get a completion signal of the data validity from the native data as contrasted with sin91e-rail. However, the dual-rail scheme suffers from large chip area and increasing of Power consumption from all signals by the switching of the return-to-zero. We need to diminish number of circuit switching. The proposed RZ/HRZ data transmission reduces a switching activity to about 50% and it shows 23% lower power consumption than the conventional dual-rail coding with RZ's.