• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1273-1276
• /
• 2007

We provide a newly developed dry etching process for the fabrication of ZnO-based oxide TFTs. The etching characteristics of ZnO (active layer) and $Al_2O_3$ (gate insulator) thin films were systematically investigated when the etching gas mixtures and their mixing ratios were varied in the heliconplasma etching system.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.222-225
• /
• 2008

We proposed the dry etching process recipe for the fabrication of In-Ga-Zn-O (IGZO)-based oxide TFTs, in which the etching behaviors of IGZO films were systematically investigated when the etching gas mixtures and their mixing ratios were varied. Good device characteristics of the fabricated TFT were successfully confirmed.

• Journal of the Korean Vacuum Society
• /
• v.6 no.3
• /
• pp.242-248
• /
• 1997

Porous silicons were prepared by dry etching as well as by chemical etching. The latter is a conventional method used by many researchers. Meanwhile, the former is a new method we developed. Also the porous silicon structure was made by E-beam lithography technique. However, due to the limit of this technique, minimum size we could produce was about 0.3 $\mu\textrm{m}$ in diameter on silicon wafer. In a new method, the porous silicon microstructure was fabricated by using Reactive Ion Etching method after covering with diamond powder on 4 inch wafer by using spin coater. In this method, diamond powder acted as a mask. The morphology of samples prepared under many different conditions were analysed be SEM and AFM. And we measured PL spectra for the samples. Based on these results, we observed the structure of a few hundreds $\AA$ in size from porous silicon which was made by dry etching with diamond powder. Also the PL peak for these samples lied around 590 nm compared to 760 nm for chemically etched porous silicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.2
• /
• pp.158-162
• /
• 2001

In this report, a new process for patterning of YBaCuO thin films, ICP(inductively coupled plasma) method, is described by comparing with existing wet etching method. Two 100㎛ wide and 2mm long YBaCuO striplines on LaAlO$_3$ substrates have been fabricated using two patterning techniques. And the properties were compared with the critical temperature and the SEM photography. Then, the critical temperatures of two samples were about 88 K, but the cross section of sample using ICP method was shaper than that using the wet etching method. ICP method can be used as a good etching technique process for patterning of YBaCuO superconductor.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.857-859
• /
• 2007

Durability of LCD glass, OA-10 and OA-21, to $SiCl_4$ and $SF_6$ gases was investigated. Reaction products are generated on the glass surface. The reaction products are reduced by changing the etching conditions. the durability of OA-10 and OA-21 to the dry etching gases is comparable.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.77-78
• /
• 2000

We verified the charged static electricity on LCD glass influences upon the etching uniformity of dry etching process by plasma. In the TFT-LCD manufacturing process, we mainly paid attention to eliminate the static electricity for TFT reliability. The static electricity caused the serious ununiformity of etching surface profile and etching rate in the dry etch process. Through our experiment on the made static electricity from -200V to -1000V, it was confirmed that the static electricity on LCD glass caused the etching rate variation of $1.5%{\sim}15%$. We recommend the etching process equipment for LCD manufacturing have to establish the soft X-ray exposure module system for eliminating the static electricity inside the loading and unloading chamber.

• Journal of Sensor Science and Technology
• /
• v.19 no.2
• /
• pp.137-141
• /
• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• ETRI Journal
• /
• v.27 no.3
• /
• pp.304-311
• /
• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.

• Journal of Sensor Science and Technology
• /
• v.16 no.2
• /
• pp.126-131
• /
• 2007

In this paper, we fabricated piezoresistive pressure sensor with dry etching technology which used ICP-RIE (inductively coupled plasma reactive ion etching) and etching delay technology which used SOI (silicon-on-insulator). Structure of the fabricated pressure sensor shows a square diaphragm connected to a frame which was vertically fabricated by dry etching process and a single-element four-terminal gauge arranged at diaphragm edge. Sensitivity of the fabricated sensor was about 3.5 mV/V kPa at 1 kPa full-scale. Measurable resolution of the sensor was not exceeding 20 Pa. The nonlinearity of the fabricated pressure sensor was less than 0.5 %F.S.O. at 1 kPa full-scale.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2015.11a
• /
• pp.180-181
• /
• 2015

본 논문에서는 ICP Poly Etcher를 이용한 Dry Etch에서 몇가지 공정조건의 변화에 따른 Etching 특성 변화를 연구하였다. 주요 가스유량들이 증가 할 때, Poly-Si 의 Etch rate는 증가 하였으며 Uniformity는 나빠진 것을 확인 할 수 있었고 다른 특성들은 특별한 변화를 보이지 않았다. 주요 Gas인 HBr의 증가는 PR(Photo Resist)와 Uniformity에 영향을 주었다. 이 논문을 통해 HBr의 유량이 Poly-Si Etching에 영향을 주는 결과를 알아 볼 수 있었고 HBr 가스의 유량 증가가 Polymer의 생성에 영향을 줘 Selectivity와 Uniformity를 증가 시킨다는 것도 확인 해 볼 수 있었다.