• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• Transactions on Electrical and Electronic Materials
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• 제17권3호
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• pp.143-145
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• 2016

In order to find suitable source and drain (S/D) electrodes for amorphous InGaZnO thin film transistors (a-IGZO TFTs), the specific contact resistance of interface between the channel layers and various S/D electrodes, such as Ti/Au, a-IZO and multilayer of a-IGZO/Ag/a-IGZO, was investigated using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes had good performance and low contact resistance due to the homo-junction with channel layer. The stability was measured with different electrodes by a positive bias stress test. The result shows the a-IGZO TFTs with a-IGZO/Ag/a-IGZO electrodes were more stable than other devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.482-491
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• 2012

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• ETRI Journal
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• 제39권2호
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• pp.284-291
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• 2017

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.451-456
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• 2014

A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.

• 한국지반공학회지:지반
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• 제14권6호
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• pp.93-112
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• 1998

본 연구에서는, 연약한 준설매립점토지반 내부에 플라스틱 배수재를 수평으로 설치하여 압밀침하의 가속화를 유도하는 수평배수공법의 해석절차 체계화에 초점을 두고 이론적 및 실험적 접근을 진행하였다. 이를 위해, 유한변형률 개념을 근거로 한 Gibson등의 1차원 자중압밀이론을 토대로, 자중압밀효과 및 수평배수재 설치에 따른 추가 압밀효과를 복합적으로 고려하는 지배방정식을 제시하였으며, 본 지배방정식 및 수평배수재 설치효과를 고려한 초기조건 및 경계조건 등을 토대로, Dufort-Erankel의 유한차분화 알고리즘을 이용해 시간경과에 따른 침하량 및 압밀도 등의 변화를 예측하기 위한 해석절차를 제시하였다. 또한 제시된 해석절차의 적용 타당성 확인을 위해, 안산 시화지구 준설매립점토 및 플라스틱 수평배수재를 이용한 실내모형실험을 실시하였다. 실내실험을 통해, 안산 시화지구 준설매립점토의 간극비-유효응력 관계 및 투수계수-간극비 관계 등을 정량적으로 정의하기 위한 기초자료를 획득 하였으며. 또한 시간경과에 따른 깊이별 침하량등을 측정하여 본 연구에서 제시된 해석절차에 의한 예측치와 비교.분석하였다. 이외에도 플라스틱 배수재 수평배수공법에 관련된 설계변수가 압밀침하등에 미치는 영향을 제시된 해석절차를 이용해 분석하였으며, 이 결과를 토대로 한 설계도표의 제시도 이루어 졌다.

• 한국경영과학회지
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• 제10권2호
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• pp.65-74
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• 1985

Domestic versus overseas postgraduate education in science and engineering has its own advantages and disadvantages. One of the issues involved in developing countries is the problem of brain drain. This study deals with the cost and benefit of domestic and foreign education, problems in brain drain and the social and private rate of return analysis in postgraduate science and technology education in Korea.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 1986년도 학술발표회 발표강연집
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• pp.21-72
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• 1986

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.