• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.878-881
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel thickness and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model.

• Korean Journal of Medicinal Crop Science
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• v.17 no.3
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• pp.204-209
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• 2009

This study was conducted to assess water movement in paddy-upland rotation soil scheduled for ginseng cultivation through the measurement of infiltration and permeability of soil water. Soil sample was divided with four soil layers. The first soil layer (to 30cm from top soil) was loamy sand, the second and the third soil layers (30$\sim$70 ㎝) were sand, and the fourth (< 120 ㎝) was sandy loam. The soil below 130 ㎝ of fourth soil layer was submerged under water. The shear strength, which represents the resisting power of soil against external force, was 3.1 kPa in the first soil layer. This corresponded to 1/8 of those of another soil layer and this value could result in soil erosion by small amount of rainfall. The rates of infiltration and permeability depending on soil layers were 39.86 cm $hr^{-1}$ in top soil, 2.34 cm $hr^{-1}$ in 30$\sim$70 ㎝ soil layer, 5.23 cm $hr^{-1}$ and 0.18 cm $hr^{-1}$ in 70$\sim$120 ㎝ soil layer, with drain tile, and without drain tile, respectively. We consider that ground water pooled in paddy soil and artificial formation of soil layer could interrupt water canal within soil and affect negatively on water movement. Therefore, we suggest that to drain at 5 m intervals be preferable when it makes soil dressing or soil accumulation to cultivate ginseng in paddy-upland rotation soil to reduce failure risk of ginseng cultivation.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.210-213
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• 1991

The clamp mode Zero-Volatge-Switched Multi-Resonant-Converter(ZVS-MRC) is proposed. In the converter, the performance of the conventional ZVS-MRC is improved by clamping the drain-to-source voltage of the power switch using a soft switching nondissipative active clamp network. The analysis for each stage of the converter operation modes is presented and is verified by experiments.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.229-232
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• 2000

In this study, An active band grass filter for 2.14GHz have been designed with MMIC using negative resistance circuit. The negative resistance element was realized with a common-drain FET with series inductive feedback. The designed active filter showed an insertion loss of 0dB at 2.14GHz and a 3-dB bandwidth of 125MHz.

• Korean Journal of Crystallography
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• v.12 no.3
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• pp.162-165
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• 2001

The EDL (Embedded DRAM and Logic) technologies with stack cell capacitors based on NO dielectric and Co-silicided source/drain junctions using a Ti capping material, were successfully implemented. The employed Co-silicided film exhibited junction leakage characteristics comparable to those of non-silicided junctions. Improved device characteristics without degradation of I/sub off/ was also achieved.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2001.09a
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• pp.227-234
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• 2001

The responses of a 1:5 scale 3-story masonry-infilled RC frame which was designed only for gravity loads were simulated by using a nonlinear analysis program, DRAIN-2DX The objective of this study is to verify the correlation between the experimental and analytical responses of masonry-infilled RC frame. It is concluded from this comparison that the strength and stillness of the whole structure can be predicted with quite high reliability using compressive strut (compression link element, Type 09) while some local behavior cannot be described reasonably.