• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.451-456
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• 2014

A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.67-75
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• 2013

In this paper, an analytical model is presented for the source/drain parasitic resistance of FinFET. The parasitic resistance is a important part of a total resistance in FinFET because of current flow through the narrow fin. The model incorporates the contribution of contact and spreading resistances considering three-dimensional current flow. The contact resistance is modeled taking into account the current flow and parallel connection of dividing parts. The spreading resistance is modeled by difference between wide and narrow and using integral. We show excellent agreement between our model and simulation which is conducted by Raphael, 3D numerical field solver. It is possible to improve the accuracy of compact model such as BSIM-CMG using the proposed model.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1870-1877
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• 1990

The electromagnetic properties of P- and n-channel split drain magnetic sensitive MOSFET fabricated using 2\ulcorner design rules and CMOS process technology has been investigated. The achieved output voltage in the double drain MOSFET was 160mV at 10\ulcorner drain current and magnetic flux density of 10kG, and the sensitivity was 1.6x10**3 V/A\ulcornerG. A further higher sensitivity was obtained by introducing a third drain in the split region. In this case, the triple drain MOSFET showed a much higher sensitivity of 2x10**3 V/A\ulcornerG under the same condition. Also, the linearity of output voltage vs. magnetic flux density was excellent.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.273-275
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• 2005

The national need to establish a new stray current mitigation method to protect the underground metallic infrastructures in congested downtown area forced us to design and develop the distributed impressed current cathodic protection (DICCP) system. The main purpose of this system is to replace the stray current drainage bond methods, which is widely adopted by pipeline owners in Korea. Currently, forced drainage makes up about 85% of total drainage facilities installed in Korea because polarized drainage can neither drain perfectly the stray currents during normal operation of electric vehicle nor drain the reverse current during regenerative braking at all. The forced drainage, however, has been abused as an alternative cathodic protection system, which impresses currents from rails to the pipelines and accordingly uses the rails as anodes. As a result, it is necessary to consider a new method to both cathodically protect the pipelines and effectively drain the stray currents. In this paper, we describe the design parameters and installation schemes of DICCP system that can meet these demands.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.102-106
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• 2012

This paper was carried out to survey fire hazard and improvement at the drain pump in air-conditioners. Based on the results of analysis, the proposal of electrical accidents prevention and a construction improvement are as follows. A power connection of the drain pump has two types, an electrical outlet type and direct connection type at control board of air-conditioner. The electrical outlet types need a bulletin sign or education as malfunction of the drain pump include an additional accidents, current leakage and overflowing with water on the floor from breaker trip by exterior cause and breaker off by mistake of worker. On the other hand, the direct connection types prevent a power interruption as exterior cause, but it has some trouble, cut of ground cable and without protection device. Usually it doesn't work by electrician when air-conditioner and the drain pump power work. Therefore an education or countermeasures are recommended for not electrician. Generally malfunction of the drain pump causes accumulated materials into the tank. Even though the accumulated materials lead to an overheating and burning as failure of detector occur an idling, periodic inspection of the air-conditioner filter and the drain pump tank prevent the trouble.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1797-1799
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• 2000

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.93-97
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• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.