• Journal of information and communication convergence engineering
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• 제7권3호
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• pp.361-365
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• 2009

This paper has been presented the transport characteristics of FinFET using the analytical potential model based on the Poisson's equation in subthreshold and threshold region. The threshold voltage is the most important factor of device design since threshold voltage decides ON/OFF of transistor. We have investigated the variations of threshold voltage and drain induced barrier lowing according to the variation of geometry such as the length, width and thickness of channel. The analytical potential model derived from the three dimensional Poisson's equation has been used since the channel electrostatics under threshold and subthreshold region is governed by the Poisson's equation. The appropriate boundary conditions for source/drain and gates has been also used to solve analytically the three dimensional Poisson's equation. Since the model is validated by comparing with the three dimensional numerical simulation, the subthreshold current is derived from this potential model. The threshold voltage is obtained from calculating the front gate bias when the drain current is $10^{-6}A$.

• 전기의세계
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• 제30권10호
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.33-39
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• 2006

나노 스케일 벌크 MOSFET의 RF 비선형 특성을 넓은 bias영역에 걸쳐 정확히 예측하기 위하여 내된 비선형 요소들을 가진 엠피리컬 비선형 모델이 새롭게 구축되었다. 먼저, 나노 스케일 벌크 MOSFET에 적합한 파라미터 추출방법을 사용하여 측정된 S-파라미터로부터 bias 종속 내부 파라미터 곡선을 추출하였다. 그 후에 비선형 캐패시턴스 및 전류원 방정식들은 추출된 bias 종속 곡선들과 3차원 fitting함으로서 엠피리컬하게 구하여졌다. 이와 같이 모델된 S-파라미터는 60nm MOSFET의 측정치와 20GHz 까지 아주 잘 일치하였으며, 이는 엠피리컬 나노 MOSFET 모델의 정확도를 증명한다

• 한국위성정보통신학회논문지
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• 제5권2호
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• pp.82-86
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• 2010

본 논문에서는 포락선추적 기능을 갖는 WCDMA 기지국에 사용될 수 있는 GaN FET를 이용한 전력증폭기 모듈을 설계하고, 제작 및 측정결과를 제시하였다. 개발된 전력증폭기 모듈은 소신호 RF 신호를 입력받아 고이득 MMIC 증폭기, 구동 증폭기 및 전력 증폭기 등을 거쳐 10W 이상의 출력을 생성할 수 있다. 또한, Envelope Tracking 응용을 위해서 최종 전력증폭기의 Drain 전압이 가변되어도 전체 모듈이 안정적으로 동작할 수 있도록 발진방지회로, Isolator, 음전압 우선인가 바이어스 회로가 설계되었다. 모든 바이어스 회로와 RF회로를 $17.8{\times}9.8{\times}2.0\;cm3$ 크기의 하우징 안에 집적화하여 소형화시켰다. 측정결과 바이어스 전압이 4V에서 28V까지 가변할 경우 30dBm에서 40dBm까지 출력이 가변되면서도 35%이상의 일정한 효율 특성을 나타내어 포락선 추적 기능을 수행할 수 있음을 확인하였다.

• ETRI Journal
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• 제16권4호
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• pp.1-11
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• 1995

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital handheld phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using $0.8{\mu}m$ design rule, showed a maximum drain current density of 330 mA/mm at $V_{gs}$ =0.5V and a gate-to-drain breakdown volt-age of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.

• 한국전기전자재료학회논문지
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• 제21권10호
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• pp.885-888
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• 2008

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

• 전기전자학회논문지
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• 제3권1호
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• pp.118-125
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• 1999

게이트 아래의 기판과 쏘오스/드레인의 접합부분 사이의 길이로 정의되는 LDD MOSFET의 metallurgical 채널 길이를 커패시턴스 측정을 이용하여 결정할 수 있는 방법을 제안하였다. 전체의 게이트 면적이 동일한 평판 모양과 손가락 모양의 LDD MOSFET 게이트 테스트 패턴의 커패시턴스를 측정하였다. 각 테스트 패턴의 쏘오스/드레인과 기판의 전압을 접지시키고 게이트의 전압을 변화시키면서 커페시턴스를 측정하였다. 두 테스트 패턴의 측정치의 차이를 그려서 최대점이 나타나는 점의 값를 간단한 수식에 대입하여 metallurgical 채널 길이를 구하였다. 이차원적 소자 시뮬레이터를 사용하여 수치해석적 모의 실험을 함으로써 제안한 방법을 증명하였다.

• 한국전기전자재료학회논문지
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• 제19권1호
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• pp.1-6
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• 2006

High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• 한국전기전자재료학회논문지
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• 제15권7호
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• pp.583-590
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• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.