• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.513-520
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• 2003

In this paper, a novel design concept of frequency doubler using feedforward technique and DGS microstrip line is proposed. The feedforward loop plays a role of fundamental frequency suppression and DGS microstrip line suppresses over the 3rd order harmonic components. By using this new concept, the high suppression for the undesired signals could be achieved easily. The proposed technique is experimentally demonstrated in 1.87 GHz-to-3.74 GHz frequency doubler. The output power of -3 dBm at the frequency of 3.74 GHz(2f$\_$0/) is measured with 42.9 dB suppression of the fundamental frequency signal(f$\_$0/), 20.2 dB suppression of the 3rd harmonic signal(3f$\_$0/) and B9.7 dB suppression of the 4th harmonic signal(4f$\_$0/). The conversion loss of -2.34 dB ∼ -5.8 dB at the bandwidth of 100 MHz, the phase noise of -97.51 dB/Hz(＠10 kHz) were measured.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.445-448
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• 2005

A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.

• Journal of Power Electronics
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• v.12 no.4
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• ETRI Journal
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• v.27 no.2
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• pp.133-139
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• 2005

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 ${\mu}$ gate-length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2mm${\times}$ 2mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1mm${\times}$ 2mm. The frequency doubler achieved an output power of -6 dBm at 76.5 GHz with a conversion gain of -16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2mm ${\times}$ 1.2mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W-band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1741-1746
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Journal of electromagnetic engineering and science
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• v.15 no.4
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• pp.232-238
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• 2015

This work describes the development of a D-band (110-170 GHz) signal source based on a SiGe BiCMOS technology. This D-band signal source consists of a V-band (50-75 GHz) oscillator, a V-band amplifier, and a D-band frequency doubler. The V-band signal from the oscillator is amplified for power boost, and then the frequency is doubled for D-band signal generation. The V-band oscillator showed an output power of 2.7 dBm at 67.3 GHz. Including a buffer stage, it had a DC power consumption of 145 mW. The peak gain of the V-band amplifier was 10.9 dB, which was achieved at 64.0 GHz and consumed 110 mW of DC power. The active frequency doubler consumed 60 mW for D-band signal generation. The integrated D-band source exhibited a measured output oscillation frequency of 133.2 GHz with an output power of 3.1 dBm and a phase noise of -107.2 dBc/Hz at 10 MHz offset. The chip size is $900{\times}1,890{\mu}m^2$, including RF and DC pads.

• Journal of Navigation and Port Research
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• v.28 no.1
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• pp.37-41
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• 2004

In this paper, a reflector type frequency doubler for local oscillator at 24GHz is designed and fabricated with ne71300-N MESFET. Optimum source and load impedances are decided through a multiharmonic load pull simulation technique. A conversion gain can be improved using the reflector and fundamental and third harmonics are well suppressed with open stub of $\lambda$/4 length Measured results show output power at 0dBm of input power is -3.776dBm, conversion gain 0.736dB, harmonic suppression 41.064dBc, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.560-566
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• 2004

In this paper, active frequency doubler with broadband characteristics from 6 ㎓ to 12 ㎓ was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed series RC circuit between bias line and input matching network far the improvement of stability. With 0 ㏈m input power, second harmonic of 1.7 ㏈m at 12 ㎓ -27.5 ㏈c suppression of 6 ㎓ fundamental, -18 ㏈c suppression of 18 ㎓ 3rd harmonic, and the 3 ㏈ output bandwidth of 1,8 ㎓ have been measured.

• Journal of Power Electronics
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• v.6 no.1
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• pp.45-51
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• 2006

A new high efficiency phase shifted full bridge (PSFB) converter for the power sustaining module of a plasma display panel (PDP) is proposed in this paper. The proposed converter employs a voltage doubler rectifier without an output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the output voltage level. No dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed. Therefore, high efficiency, as well as, a low noise output voltage can be realized. Due to the elimination of the large output inductor, it features a simple structure, lower cost, smaller mass and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell reduces the current stresses of the rectifier diodes. In this paper, operational principles, an analysis of the proposed converter and experimental results are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.561-568
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• 2011

This paper describes the operation characteristic of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS. A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of operation characteristic and controller design has not been known after the converter circuit was proposed. For the performance evaluation of PFC converter, single-phase 3kVA double-conversion UPS was tested. The performance of PFC converter is experimentally confirmed with followings - input current reference traking, input power factor correction.