• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• ETRI Journal
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• v.34 no.2
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.3
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• pp.193-199
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• 2009

Powerline communications (PLC) technology has been discussed and analyzed as a highly potential candidate of wireline access network solutions. In this paper, performance of double binary turbo coded orthogonal frequency division multiplexing (OFDM) system is analyzed and simulated in power line communications channel. In order to make power line channel environments, Bernoulli-Gaussian noise is considered. The performance is evaluated in terms of bit error probability. From the simulation results, it is demonstrated that the double binary turbo coding scheme offers considerable coding gain with reasonable encoding complexity. It is also shown that the system performance can be substantially improved by increasing the number of iterations.

• Clinical and Experimental Pediatrics
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• v.64 no.6
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• pp.269-279
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• 2021

Clustered regularly interspaced short palindromic repeats and CRISPR-associated protein 9 (CRISPR-Cas9) is an ancient prokaryotic defense system that precisely cuts foreign genomic DNA under the control of a small number of guide RNAs. The CRISPR-Cas9 system facilitates efficient double-stranded DNA cleavage that has been recently adopted for genome editing to create or correct inherited genetic mutations causing disease. Congenital heart disease (CHD) is generally caused by genetic mutations such as base substitutions, deletions, and insertions, which result in diverse developmental defects and remains a leading cause of birth defects. Pediatric CHD patients exhibit a spectrum of cardiac abnormalities such as septal defects, valvular defects, and abnormal chamber development. CHD onset occurs during the prenatal period and often results in early lethality during childhood. Because CRISPR-Cas9-based genome editing technology has gained considerable attention for its potential to prevent and treat diseases, we will review the CRISPR-Cas9 system as a genome editing tool and focus on its therapeutic application for CHD.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.39-46
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• 1999

In this paper, we propose new hardware architecture of a fast searcher for an initial code acquisition in wideband CDMA wireless local loop systems. The proposed searcher uses double-dwell serial search algorithm and has N active correlators for the high performance code acquisition. Since the N active correlators are designed with pipelined architecture, it is possible to reduce the hardware complexity with only one energy calculation. Our architecture is designed using VHDL to meet wideband CDMA wireless local loop standard and verified under JTC wideband channels. Average code acquisition time of the proposed fast searcher which has 16 correlators is about 40 seconds in case of initial installation and 0.16 seconds when a base station is known. The verified fast searcher is synthesized with in $0.6\mu\textrm{m}$ LG library. The synthesized searcher has 15.8K rates when the number of 4he correlators is 16.