• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.804-810
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• 2005

An analytical subthreshold swing (SS) model has been presented for double gate MOSFET(DGMOSFET) in this study. The results calculated by this model are more precise for about 10nm channel length and thickness than those derived from the previous models. The results of this model are compared with Medici simulation to varify the validity of this model, and good agreementes have been obtained. The changes of SS have been investigated for various channel lengths, channel thicknesses and gate oxide thicknesses using this model, given that these parameters are very important in design of DGMOSFET. This demonstrates that the proposed model provides useful data for design of nano-scale DGMOSFET. It is Known that the SS is improved to smaller ratios of channel thickness vs channel length and is smaller in very thin oxides. New gate dielectric materials with high permittivity have to be developed to enable design of nano-scale DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2643-2648
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• 2015

This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.583-586
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• 2011

In this paper, subthreshold swing characteristics have been presented for double-gate MOSFETs, using the analytical model based on series form of potential distribution. Subthreshold swing is very important factor for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec. The channel length $L_g$ is varied from 30nm to 100nm, and channel thickness $t_{si}$ from 15 to 20nm according to channel length, and oxide thickness 5nm to investigate subthreshold swing. The doping of channel is fixed with $10^{16}cm^{-3}$ p-type. The results show good agreement with numerical simulations, confirming this model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.121-126
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• 1996

In this paper an MMIC VCO which can be used in a double conversion TV tuner is designed, fabricated and measured. The VCO is designed using the small signal method and fabricated using ETRI GaAs MMIC foundry. The 3x200$\mu$m gate width MESFET with 1$\mu$m gate length is used for an active device and MIM capacitors, spiral inductors, thin film resitors are used as passive elements. The VCO has output power of 10.95dBm at 1955 MHz with 5V bias voltage and 4V tuning voltage. The oscillation frequency change form 1947 MHz to 1964 MHz is obtaine dby an external varactor diode connected to the gate with a tuning voltage from 0 V to 6V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.992-997
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• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.579-584
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.888-891
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.