• Journal of IKEEE
• /
• v.14 no.4
• /
• pp.297-304
• /
• 2010

This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.11
• /
• pp.27-33
• /
• 2011

Recently many display devices support the digital display interface as display market growth. DisplayPort is a next generation display interface at the PC, projector and high definition content applications in more widely used connection solution development. This paper implements multiple streams based on the behavior of the main link that is suitable for the display port v1.1a standard. The limit point of Displayport, interface between the Sink Device and Sink Device is also implemented. And two or more differential image data are enable to output the result through four Lanes stated in display port v1.1a, of two or more display devices without the addition of a separate Lane. The Multiple Video Streaming Controller is implemented with 6,222 ALUTs and 6,686 register, 999,424 of block memory bits synthesized using Quartus II at Altera Audio/Video Development board (Stratix II GX FPGA Chip).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.282-290
• /
• 2013

This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a $0.13{\mu}m$ CMOS technology.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.40-46
• /
• 2010

This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

• Journal of Navigation and Port Research
• /
• v.31 no.8
• /
• pp.637-643
• /
• 2007

In many fields, commercial programs or equipments are biting developed and these are getting complicated more and more by adding advantages from existing products. In promoting the usability of these products, design based on the information integration receives attention. However, is information integration always better? In this study, we tried to demonstrate information distribution is more efficient than information integration through conning display design that was propelled by many countries' classification societies. We designed the conning display using many ergonomic methods and conducted its performance experiment. Results of the performance experiment reveal that conning display having two modes (one shows the functions related with ocean and coast voyage and another shows the functions related with docking and leaving port) is more efficient.

• Journal of IKEEE
• /
• v.15 no.2
• /
• pp.113-121
• /
• 2011

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.3
• /
• pp.185-192
• /
• 2013

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at $2^{31}$-1 PRBS is measured to 7/5.6/4.7 $ps_{rms}$, respectively, while consuming 11 mW from a 1.2 V supply.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• 1995.11a
• /
• pp.118-124
• /
• 1995

This paper describes the research and development of the Electronic Chart Data base and the Electronic Chart Display and Information System(ECDIS) based on the Draft Soecification for ECDIS of IHO by the Research Group on ECDIS of the Ministry of Communicatios of China, The paper also briefly introduces the systems configuration basic function electronic chart data base of China and the future prospects.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.7
• /
• pp.68-73
• /
• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.1-7
• /
• 2010

This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.