전기전자학회논문지 (Journal of IKEEE)

  • 제14권4호
  • /
  • Pages.297-304
  • /
  • 2010
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지

A Link Layer Design for DisplayPort Interface

  • 투고 : 2010.12.03
  • 심사 : 2010.12.29
  • 발행 : 2010.12.30
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초록

This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.

키워드

참고문헌

  1. VESA, "VESA DisplayPort Standard", Version 1, Revision 1a, January 11, 2008.
  2. VESA, "DisplayPort Link Layer Compliance Test Standard", Version 1.0, September 14, 2007.
  3. CEA, A DTV Profile for Uncompressed High Speed Digital Interfaces, CEA-861-C, pp69-74, August 2005.
  4. IEC, Digital Audio Interface - part1 : general, IEC 60958-1, September 2008.
  5. IEC, Digital Audio Interface - part3 : Consumer application, IEC 60958-3, May 2006.