Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지

A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in $0.18{\mu}m$ CMOS

  • Received : 2010.05.04
  • Published : 2010.04.26
Download PDF
⟨ Previous Next ⟩

Abstract

This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

Keywords

References

  1. VESA, DisplayPort Standard, Version 1, Revision 1a, January 2007.
  2. L. Henrickson, et al., "Low-Power Fully Integrated 10-Gb/s SONET/SDH Transceiver in 0.13-$\mu{m}$ CMOS," IEEE Journal of Solid-State Circuits, vol.38, no.10, pp.1595-1601, October 2003. https://doi.org/10.1109/JSSC.2003.817586
  3. B. Razavi, Design of Analog CMOS Integrated Circuits, New York, McGraw-Hill, pp.482-531, 2001.
  4. J. Savoj, B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit with a half-Rate Binary Phase/Frequency Detector," IEEE Journal of Solid-State Circuits, vol.38, no.1, pp. 13-21, January 2003. https://doi.org/10.1109/JSSC.2002.806284
  5. Chorng-Sii Hwang, et al., "Dual-Band CDR using a Half-Rate Linear Phase Detector," IEEE International of SOC Conference, pp.51-54, September 2009.