• Title/Summary/Keyword: Direct-conversion mixer

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A multistandard CMOS mixer using switched inductor (스위칭 인덕터를 이용한 다중 표준용 CMOS 주파수 변환기)

  • Yoo, Sang-Sun;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.3 s.357
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    • pp.78-84
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    • 2007
  • A multistandard direct-conversion mixer for WCDMA, Wibro, and 802.11a/b/g is designed in 0.18 um CMOS technology To support multistandard and to reduce the chip area the switched inductor is used as the matching method. This switched inductor matching network selects the mixer's operation frequency band by turning on or off the switch transistor. Since the performances of mixer and operation frequency can be affected by the parasitic of switch transistor the mixer should be designed with the optimized size of switch to minimize parasitic effects. Proposed mixer is able to achieve return loss less than -13 dB in $2.1\sim2.5GHz$ and $5.1\sim5.9GHz$ bands with the suitable performance to meet requirements of WCDMA, WiBro, and 802.11a/b/g.

A 2.4-GHz Low-Power Direct-Conversion Transmitter Based on Current-Mode Operation (전류 모드 동작에 기반한 2.4GHz 저전력 직접 변환 송신기)

  • Choi, Joon-Woo;Lee, Hyung-Su;Choi, Chi-Hoon;Park, Sung-Kyung;Nam, Il-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.91-96
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    • 2011
  • In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

A CMOS Fully Integrated Wideband Tuning System for Satellite Receivers (위성 수신기용 광대역 튜너 시스템의 CMOS 단일칩화에 관한 연구)

  • Kim, Jae-Wan;Ryu, Sang-Ha;Suh, Bum-Soo;Kim, Sung-Nam;Kim, Chang-Bong;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.7-15
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    • 2002
  • The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

DDS를 이용한 중단파대 국ㆍ영문용 DSC/NBDP 개발에 관한 연구

  • 유형열;김기문
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.4
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    • pp.805-817
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    • 1999
  • In this paper, the needs for introduction and adoption of MㆍHF DSC/NBDP system and for developments of its circuits and call sequences for use in the maritime mobile services for small-ships, leisure-ships and fishing ships are analyzed, discussed. Also design and implement for MㆍHF(1.6-4MHz) DSC/NBDP system is discussed. Most of casualties have been arisen from small-ships and fishing ships during last 5 years. So, the SAR schematic plans should been prepared to prevent casualties and facilitate the activities of SAR for those ships. DSC/NBDP for MㆍHF system is able to fulfill the roles of efficient SAR communication functions, and to advance the SAR system to small ships and fishing ships. This study is focused on the techniques of processing the DSC call sequences and the ARQ sequences of NBDP system. Especially ARQ sequences are expanded into processing of Korean letters, designed the call sequences and code conversion algorithm for Korean-code. It will be evaluated the availability of Korean-NBDP system. In designing the Transmitting circuits and Receiving circuits, for the carrier generation, DDS(Direct Digital Synthesizer) is used in stead of the Phase Locked Loop and frequency conversion by the mixer, BPF. And PSK modulation signals are directly generated by the controls of DDS, which show the characteristics of Spurious Free Dynamic Range are below -62dBc. Also, the monolithic U subsystem IC which provides various functional components, AD608 is used for designing the receiving circuitsㆍAnd the algorithm of Phasing methode for FSK demodulation are devised to process IF frequency 455kHz in the IF circuits.

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The Design of CMOS Multi-mode/Multi-band Wireless Receiver

  • Hwang, Bo-Hyeon;Jeong, Jae-Hun;Yu, Chang-Sik
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.615-616
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    • 2006
  • Nowadays, the need of multi-mode/multi-band transceiver is rapidly increasing, so we design a direct conversion RF front-end for multi-mode/multi-band receiver that support WCDMA/CDMA2000/WIBRO standard. It consists of variable gain reconfigurable LNA and single input double balanced Mixer and complementary differential LC Oscillator. The circuit is implemented in 0.18 um RF CMOS technology and is suitable for low-cost mode/multi-band.

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A Study on the Data Transmission line of communication system (통신시스템의 데이터 전송선로에 대한 연구)

  • Kim Soke-Hwan;Lee Kyeu-jung;Hur Chang-wu
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.6
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    • pp.1277-1281
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    • 2005
  • FPGA has been widely used in communication system. In this paper, we made 10 layers PCB on protection of signal noise and data lose with FPGA. We analyzed about change of the data transmission speed and length according to input frequency. The length of transmission line from FPGA's output-pin to output-port on PCB board is 13cm and extended lengths for test are 30cm, 60cm and 10cm. We knew that data can be stably transmitted to 100Mbps at transmission line length of 30cm.

A Wideband Down-Converter for the Ultra-Wideband System (초광대역 무선통신시스템을 위한 광대역 하향 주파수 변환기 개발에 관한 연구)

  • Kim Chang-Wan;Lee Seung-Sik;Park Bong-Hyuk;Kim Jae-Young;Choi Sang-Sung;Lee Sang-Gug
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.2 s.93
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    • pp.189-193
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    • 2005
  • In this paper, we propose a direct conversion double-balanced down-converter fer MB-OFDM W system, which is implemented using $0.18\;{\mu}m$ CMOS technology and its measurement results are shown. The proposed down-converter adopts a resistive current-source instead of general transconductance stage using MOS transistor to achieve wideband characteristics over RF input frequency band $3\~5\;GHz$ with good gain flatness. The measured conversion gain is more than +3 dB, and gain flatness is less than 3 dB for three UWB channels. The dc consumption of this work is only 0.89 mA from 1.8 V power supply, leading to the low-power W application.

A 2.3-2.7 GHz Dual-Mode RF Receiver for WLAN and Mobile WiMAX Applications in $0.13{\mu}m$ CMOS (WLAN 및 Mobile WiMAX를 위한 2.3-2.7 GHz 대역 이중모드 CMOS RF 수신기)

  • Lee, Seong-Ku;Kim, Jong-Sik;Kim, Young-Cho;Shin, Hyun-Chol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.51-57
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    • 2010
  • A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

A Study on the Mobile Communication System for the Ultra High Speed Communication Network (초고속 정보통신망을 위한 이동수신 시스템에 관한 연구)

  • Kim, Kab-Ki;Moon, Myung-Ho;Shin, Dong-Hun;Lee, Jong-Arc
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.1-14
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    • 1998
  • In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

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Design of QPSK Demodulator Using CMOS BPSK Receiver and Reflection-Type Phase Shifter (CMOS 기반 BPSK 수신기와 반사형 위상 천이기를 이용한 QPSK 복조기 설계)

  • Moon, Seong-Mo;Park, Dong-Hoon;Yu, Jong-Won;Lee, Moon-Que
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.8
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    • pp.770-776
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    • 2009
  • We propose and demonstrate an I/Q demodulator using four-port BPSK demodulator base on additive mixing and reflection-type phase shifter using hybrid technique. Previously, the conventional I/Q demodulator base on multiplicative or additive mixing method divides I/Q signal path from mixer to parallel-to-serial converter. In this paper, we propose new I/Q demodulator without dividing I/Q baseband signal path. The proposed schematic requires half size in implementation and half power consumption in baseband path compared with the conventional receiver. Also, the proposed receiver eliminates parallel-to-serial converter after data decoding. The proposed circuit has been successfully demodulated a QPSK signal with the L-band carrier frequency and 20 Mbps data rate.