• 한국표면공학회지
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• 제34권1호
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• pp.33-38
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• 2001

10cm-diameter Si(100)∥$1.3\mu\textrm{m}$-X$1.3_2$X$1.3\mu\textrm{m}$-$SiO_2$∥Si(100) afers were prepared using a fast linear annealing (FLA) equipment. 1.3$\mu\textrm{m}$-thick $SiO_2$ films were grown by dry oxidation process. After cleaning and premating the wafers in a class 100 clean room, they were heat treated using with the FLA and conventional electric furnace. Bonded area and bond strength of wafer pairs were measured using a infrared (IR) camera and razor blade crack opening method, respectively. It was confinmed that the bonded area by FLA was around 99% and the bond strength value reached 2172mJ/$\m^2$, which is equivalent to theoritical bond strength. Our result implies that thick $SiO_2$ SOI may be prepared more easily by using $SiO_2$$SiO_2$ bonding interfaces then those of Si/$SiO_2$'s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.227-229
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• 1995

Using thermal oxide SiO$_2$ as a dielectrical isolation layer, SOI Hall sensors without pn junction isolation have been fabricated on Si/SiO$_2$/Si structures. The SOI structure was formed by SDB (Si- wafer direct bonding) technology. The Hall voltage and the sensitivity of Si Hall devices implemented on the SDB SOI structure show good linearity with respect to the appled magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average 600V/V.T. In the trmperature range of 25 to 300$^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the Product Sensitivity) are less than ${\pm}$ 6.7x10$\^$-3/ C and ${\pm}$8.2x10$\^$04/$^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of Hall sensors with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• 한국전기전자재료학회논문지
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• 제13권12호
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.739-742
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• 2002

This paper described on the fabrication of microstructures by DRIE(deep reactive ion etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing($1000^{\circ}C$, 60 min.), The SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as an accurate thickness control and a good flatness.

• 센서학회지
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• 제13권3호
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• pp.175-181
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• 2004

A pressure sensor for high temperature was fabricated by using a SDB(Silicon-Direct-Bonding) wafer with a Si/$SiO_{2}$/ Si structure. High pressure sensitivity was shown from the sensor using a single crystal silicon of the first layer as a piezoresistive layer. It also was made feasible to use under the high temperature as of over $120^{\circ}C$, which is generally known as the critical temperature for the general silicon sensor, by isolating the piezoresistive layer dielectrically and thermally from the silicon substrate with a silicon dioxide layer of the second layer. The pressure sensor fabricated in this research showed very high sensitivity as of $183.6{\mu}V/V{\cdot}kPa$, and its characteristics also showed an excellent linearity with low hysteresis. This sensor was usable up to the high temperature range of $300^{\circ}C$.

• 한국전기전자재료학회논문지
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• 제14권4호
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• pp.263-268
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• 2001

This paper describes the effects of applied bias conditions on electrochemical etch-stop characteristics. THere are a number of key issues such as diode leakage and ohmic losses which arise when applying the conventional 3-electrochemical etch-stop to fabricated some of he MEMS(microelectro mechanical system) and SOI(Si-on-insulator) structures which employ SDB(Si-wafer direct bonding). This work allows to perform anin situ diagnostic to predict whether or not an electrochemical etch-stop would fail due to diode-leakage-induced premature passivation. In addition, it presents technology which takes into account the effects of ohmic losses and allows to calculate the appropriate bias necessary to obtain a successful electrochemical etch-stop.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.557-560
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• 2000

Combination of SDB(Si-wafer Direct Bonding) and electrochemical etch-stop in TMAH anisotropic etchant can be used to create a variety of MEMS(Micro Electro Mechanical System). Especially, fabrication of SDB SOI structures using electrochemical etch-stop is accurate method to fabrication of 3D(three-dimensional) microstructures. This paper describes on the fabrication of SDB SOI structures with sealed cavity for MEMS applications and thickness control of active layer on the SDB SOI structure by electrochemical etch-stop. The flatness of fabricated SDB SOI structure is very uniform and can be improved by addition of TMAH to IPA and pyrazine.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.25-29
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• 2002

기존 홀 센서의 단점을 개선하기 위해서 트랜치를 이용한 수직 홀 센서를 제작하였다. 수직 홀 센서는 센서의 칩 표면에 수평 자계를 검출할 수 있으며, 홀 센서는 실리콘 직접 본딩 기술에 의해 제작된 SOI 기판 위에 제작하였다. 기판 아래의 $SiO_2$층과 마이크로머시닝에 의한 트랜치가 홀 센서의 동작 영역을 정의한다. 홀 센서의 감도는 150V/AT로 측정되었으며 안정된 값을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.579-582
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• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.