• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1677-1685
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• 2001

In this paper, we propose a call admission control scheme that can be performed within guaranteeing of required QoS(Quality of Services) in DS-CDMA(Direct Sequence-Code Division Multiple Access) reverse link. It has been performed rely on a physical channel numberonly and based on quality of received signal from MODEM(modulator/demodulator) part in established study. In other methods, the standard for services would have been set from statistical analysis of users\` location and using received power level in BTS(Base Transceiver Station). These ways bring about not only system loads but time delay or great differences from real environment. To solve these problems, we propose a call drop rate estimation algorithm for the purpose of call admission control based on measured value at LNA(Low Noise Amplifier) ports of BTS(Base Transceiver Station) in real time. This method proposed in this paper estimates a quality of offered service in real time, reduce system loads and shorten time delay which is needed to determine the standard for call admission control. But it requires a additional 17W complexity which can measure received signal power in BTS and estimate call drop rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.725-734
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• 2006

As a sequel to Part 1, the performance characteristics of the cell averaging (CA), greatest of (GO), and smallest of (SO) constant false alarm rate (CFAR) processors in nonhomogeneous environment are obtained and compared when receiving antenna diversity is employed in the pseudonoise (PN) code acquisition of direct-sequence code division multiple access (DS/CDMA) systems. Unlike in homogeneous environment, the GO CFAR processor is observed to exhibit the best performance in nonhomogeneous environment, with the CA CFAR processor performing the second best.

• Management & Information Systems Review
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• v.3
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• pp.201-214
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• 1999

Adaptive correlator receiver with neural network based on complex multilayer perceptron is persented for suppressing interference of narrow-band of direct spread spectrum communication systems. Recursive least square algorithm with backpropagation error is used for fast convergence and better performance in adaptive correlator scheme. According to signal noise and transmission power, computer simulation results show that bit error ratio of adaptive correlator using neural network improved that of adative transversal filter of direct sequence spread spectrum considering of jamming and narrow-band interference. Bit error ratio of adaptive correlator with neural network is reduced about 10-1 than that of adaptive transversal filter where interference versus signal ratio is 5dB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.154-158
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• 2003

In this paper, Error rate performance of BCH coded DS-CDMA 16 QAM signal is analyzed using selective combining Diversity reception techniques in the environments of Rician fading. First in the performance of DS-CDMA 16 QAM signal in Rician fading channel, Second using SC diversity recepting techniques, and third using both diversity and BCH coding error rate performance is evaluated. from the results of Numerical analyzed it is found that a synergistic performance improvement is shown due to both diversity reception and coding techniques overcoming mobile wireless data communication channel environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1109-1112
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• 2005

In this paper, we evaluate the performance of pilot channel-aided channel estimation for multicarrier direct-sequence (DS) code division multiple access (CDMA) communication system as proposed by Kondo and Milstein [1]. We investigate the optimum number of pilot channels for various coherence bandwidths and different number of subchannels. Keeping the total transmit bandwidth fixed, an optimum number of total subchannels and pilot channels exists under specific channel and transmitted energy. We show that there is a tradeoff between the number of pilot channels and data subchannels, thereby requiring differing numbers of optimum pilot channels according to channel conditions.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1962-1965
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• 2004

In this paper, the new algorithm for blind adaptive decorrelating parallel interference canceller detector in direct-sequence code division multiple access (DS-CDMA) synchronous communication systems is proposed. The goal of this paper is to improve the performance of the blind adaptive decorrelating parallel interference cancellation detector (BAD/PIC). The proposed blind adaptive decorrelating detector is using optimum step-size technique bootstrap algorithm as an initial stage of PIC, which does not require a training sequence. Therefore, this algorithm has a superior view of utilizing bandwidth and reduces the complexity of computation of inversion cross-correlation matrix. The computer simulation results show that the bit error rate performance of the proposed algorithm for the new structure of detector is better than that of the other detectors such as matched filters, the conventional PIC, and the blind adaptive decorrelating PIC detector.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.196-203
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• 1999

In this paper, the DS(direct sequence)-CDMA and MC(multi-carrier)-CDMA, which are being researched recently as a synchronous IMT-2000 scheme for next-generation mobile multimedia communications, are studied in terms of BER(bit error rate) performance. The BER performance of MC-CDMA with EGB, MRC, and improved MMSEC detection scheme are analyzed and compared to that of conventional DS-CDMA adopting RAKE receiver through the computer simulations under the environments of synchronous IMT-2000 transmission channel. Not only single user case but also multiuser case is considered in the given system. As a result, it is shown that MC-CDMA with MMSEC detection outperforms all other schemes improved the $E_b/N_o$ by about 5 [dB] and 6 [dB] when the BER is $2{\times}10^{-3}$, for the indoor/outdoor fading channel and synchronous IMT-2000 transmission channel, respectively. Also in the multiuser case, MC-CDMA with MMSEC detection scheme exhibits better performance than all the other schemes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.33-36
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• 2000

DS-CDMA (direct sequence-code division multiple access) 시스템에서 여러 사용자가 동일 주파수 대역을 공유함으로써 다중 접속 간섭 (multiple access interference; MAI)이 발생하고 시스템의 성능을 크게 제한한다. 이러한 다중 접속 간섭을 제거하여 전송 신호의 질을 높이고 용량을 증대시키는 중요한 신호 처리 기술 가운데 하나가 적응 간섭 억제 기술이다. 적응 간섭 억제 기술 가운데 CMA (constant modulus algorithm) 기반의 블라인드 적응 간섭 억제기는 훈련수열을 필요로 하지 않고 빠른 수렴을 통하여 간섭을 효과적으로 제거할 수 있으나, 다중 경로 환경에서 심벌간 간섭 (intersymbol interference; ISI)이 증대되어 기존의 적응 수신기보다 악화된 성능을 보인다. 본 논문에서는 CMA를 기반으로 훈련 수열 없이 빠른 수렴을 하며 MAI와 ISI를 효과적으로 제거하기 위한 다이버시티 결합기 구조의 적응 간섭 억제기를 제한한다. 다중 경로 페이딩 채널 환경에서 기존의 블라인드 적응간섭 억제기와의 성능 비교 결과, 제안된 방식이 다중경로에 의한 ISI의 영향을 효과적으로 제거하여 우수한 성능을 얻을 수 있음을 확인하였다.