• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.22-29
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• 2006

In this paper, we present the efficient way of SDRAM accessing through the DMA(Direct Memory Access) when a microprocessor and peripheral blocks are sharing a SDRAM. The microprocessor is able to access a memory through the AMBA which is the system bus provided by ARM Corporation and DMAs are able to access a memory through their own bus. Peripheral block's reading and writing on the SDRAM memory are realized by the intermediate DMA in order to minimize times of access and addressing the memory. While the microprocessor doesn‘t access to the SDRAM aproaching other registers or occurring a hit signal for fetching program or data, the DMAs may read/write the data in the SDRAM without an interference of the AMBA. This way increases the efficient of the system and performance is more by 16.8%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.445-452
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• 2010

In this paper, an attempt has been made to design the controller applicable for H.264 level3 encoder of baseline profile on full hardware basis. The designed controller module first stores the images supplied from CMOS Image Sensor(CIS) at main memory, and then reads or stores the image data in macroblock unit according to encoder operation. The timing cycle of the DMA controller required to process a macroblock is 478 cycles. In order to verify the our design, reference-C encoder, which is compatible to JM 9.4, is developed and the designed controller is verified by using the test vector generated from the reference C code. The number of cycle in the designed DMA controller is reduced by 40% compared with the cycle of using Xilinx MIG.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.91-94
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• 2008

The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.822-828
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• 2019

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.606-613
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• 2018

This study is concerned with implementing an external memory expansion device for large-scale image processing. It consists of an external memory adapter card with a PCI(Peripheral Component Interconnect) Express Gen3 x8 interface mounted on a graphics workstation for image processing and an external memory board with external DDR(Dual Data Rate) memory. The connection between the memory adapter card and the external memory board is made through the optical interface. In order to access the external memory, both Programmable I/O and DMA(Direct Memory Access) methods can be used to efficiently transmit and receive image data. We implemented the result of this study using the boards equipped with Altera Stratix V FPGA(Field Programmable Gate Array) and 40G optical transceiver and the test result shows 1.6GB/s bandwidth performance.. It can handle one channel of 4K UHD(Ultra High Density) image. We will continue our study in the future for showing bandwidth of 3GB/s or more.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.32-37
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• 1982

This paper shows a design method of English/Hanguel/Chinese display controller using address conversion thchnique and DMA in the raster scanning graphic CRT display by giving a design example (64 characters$\times$16 lines display controller).

• Journal of the KSME
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• v.25 no.2
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• pp.137-140
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• 1985

이글에서는 마이크로프로세서의 원리와 응용에 관하여 다음의 사항을 중심으로 알아보았다. 1. 마이크로프로세서의 작동원리 - 인텔 8086, 기타 마이크로 프로세서의 작동 (1) 인터럽트(Interrupt) (2) 대기(wait) (3) DMA(Direct Memory Access)

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.33-41
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• 2014

This paper presents an effective memory access method for a high-speed data transfer on mobile systems using a direct memory access controller that considers the characteristics of a multi-port memory controller. The direct memory access controller has an integrated channel management function to control multiple direct memory access channels. The channels are physically separated and operate independently from each other. Experimental results show that the proposed direct memory access method improves the transfer performance by up to 72% and 69% on read and write transfer cycles, respectively. The total number of transfer cycles of the proposed method is 63% less than in a commercial method under 4-channel access.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.11
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• Journal of Sensor Science and Technology
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• v.15 no.4
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• pp.223-230
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• 2006

An FIR filter for digital voice signal processing has been designed and implemented using a microcontroller in implantable middle ear hearing devices (IMEHDs). The designed digital voice signal processing filter which has fast and accurate filtering operation and controllable filter characteristics has been implemented using a hardware multiplier and a direct memory access (DMA) in the low power microcontroller, MSP430F169. It has been confirmed that each of the implemented 6-orders Remez FIR filters with 1 channel and 2 channels can be applied to the voice signal processing module of IMEHDs based on the evaluation results of the filtering performance experiment.