• 제목/요약/키워드: Digital time delay

검색결과 435건 처리시간 0.043초

동작온도에 무관한 신호변환회로의 설계 (Design of Temperature Stable Signal Conversion Circuit)

  • 최진호;김수환;임인택;최진오
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 춘계학술대회
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    • pp.671-672
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    • 2011
  • 지연소자를 이용하여 시간정보를 디지털 정보로 변환하는 회로를 설계하였다. 지연소자로는 아날로그 회로 혹은 디지털 회로로 구성할 수 있으나, 아날로그 지연소자의 경우 디지털 지연소자에 비해 공정 변화에 따른 신뢰성 면에서 우수한 특성을 가지므로 본 논문에서는 전류원 회로와 인버터를 이용하여 아날로그 형태로 지연소자를 구성하였다. 설계되어진 회로는 동작온도가 $-20^{\circ}C$에서 $70^{\circ}C$까지 변화하더라도 출력 특성의 변화가 없도록 설계되어졌으며, HSPICE 시물레이션을 이용하여 동작을 확인하였다.

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Feasibility study of multiplexing method using digital signal encoding technique

  • Kim, Kyu Bom;Leem, Hyun Tae;Chung, Yong Hyun;Shin, Han-Back
    • Nuclear Engineering and Technology
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    • 제52권10호
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    • pp.2339-2345
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    • 2020
  • Radiation imaging systems consisting of a large number of channels greatly benefit from multiplexing methods to reduce the number of channels with minimizing the system complexity and development cost. In conventional pixelated radiation detector modules, such as anger logic, is used to reduce a large number of channels that transmit signals to a data acquisition system. However, these methods have limitations of electrical noise and distortion at the detector edge. To solve these problems, a multiplexing concept using a digital signal encoding technique based on a time delay method for signals from detectors was developed in this study. The digital encoding multiplexing (DEM) method was developed based on the time-over-threshold (ToT) method to provide more information including the activation time, position, and energy in one-bit line. This is the major advantage of the DEM method as compared with the traditional ToT method providing only energy information. The energy was measured and calibrated by the ToT method. The energy resolution and coincidence time resolution were observed as 16% and 2.4 ns, respectively, with DEM. The position was successfully distributed on each channel. This study demonstrated the feasibility that DEM was useful to reduce the number of detector channels.

Field Programmable Gate Array 기반 다중 클럭과 이중 상태 측정을 이용한 시간-디지털 변환기 (Time-to-Digital Converter Implemented in Field-Programmable Gate Array using a Multiphase Clock and Double State Measurements)

  • 정현철;임한상
    • 전자공학회논문지
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    • 제51권8호
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    • pp.156-164
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    • 2014
  • Field programmable gate array 기반 시간-디지털 변환기(Time to Digital Converter)로 가장 널리 사용되는 딜레이 라인(tapped delay line) 방식은 딜레이 라인의 길이가 길어지면 정확도가 떨어지는 단점이 있다. 이에 본 논문에서는 동일한 시간 해상도를 가지면서 딜레이 라인의 길이를 줄일 수 있도록 4 위상 클럭을 사용하고 이중 상태 판별 제어부를 가지는 시간-디지털 변환기 구조를 제안한다. 4 위상 클럭 별로 딜레이 라인 구성 시 발생하는 라인 간 딜레이 오차를 줄이기 위해 입력신호와 가장 가까운 클럭과의 시간 차이만 하나의 딜레이 라인으로 측정하고 어떤 위상 클럭이 사용되었는지를 판별하는 구조를 가졌다. 또한 싱크로나이저 대신 이중 상태 측정 state machine을 이용하여 메타스태이블을 판별함으로써, 싱크로나이저로 인한 딜레이 라인의 증가를 억제하였다. 제안한 시간-디지털 변환기(TDC)의 성능 측정 결과 1 ms의 측정 시간 범위에 대해 평균 분해능 22 ps, 최대 표준편차 90 ps을 가지며 비선형성은 25 ps였다.

견실한 비선형 마찰보상 이산제어 - 이론 (Robust Digital Nonlinear Friction Compensation - Theory)

  • 강민식;김창제
    • 한국정밀공학회지
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    • 제14권4호
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    • pp.88-96
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    • 1997
  • This paper suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteresis nonlinear element which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. A proper Lyapunov function is selected and the Lyapunov direct method is used to prove the asymptotic stability of the suggested control.

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견실한 비선형 마찰보상 이산제어 (Robust Digital Nonlinear Friction Compensation)

  • 강민식;송원길;김창재
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1996년도 추계학술대회 논문집
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    • pp.987-993
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    • 1996
  • This report suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteric nonlinear clement which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. The Lyapunov direct method is used to prove the asymtotic stability of the suggested control, and the stability and the effectiveness are verified analytically and experimentally on a single axis servo driving system.

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Linearity improvement of UltraScale+ FPGA-based time-to-digital converter

  • Jaewon Kim;Jin Ho Jung;Yong Choi;Jiwoong Jung;Sangwon Lee
    • Nuclear Engineering and Technology
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    • 제55권2호
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    • pp.484-492
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    • 2023
  • Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

디지털 제어 시스템의 연산시간 지연을 고려한 예측전류제어기에 관한 연구 (A Study on the Predictive Current Controller with the Compensation of Computation Time Delay in a Digital Control Systems)

  • 우명호;정승기
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 하계학술대회 논문집 F
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    • pp.2028-2032
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    • 1997
  • When a high performance current control is desired, a computation time delay of a digital control system may deteriorate the control performance of a current controller. Such a non-negligible effect can be considerable in transient state. This paper deals with the modified predictive current control that compensates the time delay effects of a conventional predictive current control. The method is closely related to a local average current control and a symmetrical PWM pattern generation. Also some theoretical approaches are presented to describe the voltage saturation boundary of the power converter. For validation, the proposed method is applied to an active power filter system. The experimental results show considerable improvement in current tracking capability.

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P2P 오버레이 네트워크에서 효과적인 Peer 검색을 위한 B-Chord (Effective B-Chord look-up peer in P2P overlay network)

  • 홍록지;문일영
    • 디지털산업정보학회논문지
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    • 제7권4호
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    • pp.1-6
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    • 2011
  • In this paper, search-efficient Bi-directional-Chord(B-Chord) is proposed in P2P (peer-to-Peer) overlay network. Chord is the most popular P2P Look-up protocol. However, it applied to the mobile environment, the search success rate become lower and the request delay time increases. That is big problem. Thus, by improving the existing Chord, in this paper proposed B-Chord reduces the request delay time to in a mobile environment. Proposed B-Chord have the two Finger table and can search by selecting Finger table depending on the value of Key. By use these bi-directional, it can reduce the number of nodes Hop and search delay time. Thus, As a result, it will be able to increase the search success rate in a mobile environment.

동적전압보상기의 과도특성을 개선하기 위한 디지털방식의 전향제어기 설계 (Design of the Feed Forward Controller in Digital Method to Improve Transient Characteristics for Dynamic Voltage Restorers)

  • 김효성;이상준;설승기
    • 전력전자학회논문지
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    • 제9권3호
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    • pp.275-284
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    • 2004
  • 본 논문은 동적전압보상기(DVR)의 제어를 위한 우수한 성능의 디지털제어기를 제시하고 제어이득(Control Gain)의 설정에 관하여 논한다. DVR계통의 전력회로를 분석하여 DVR의 운전한계를 찾고 그에 따른 제어목표 및 제어기 구조를 제시한다. 디지털 제어기는 인버터의 PWM 스위칭과 함께 제어시스템의 시간지연을 야기한다. 이러한 시간 지연은 제어시스템의 전달함수를 1차수 높게 하여 제어시스템을 더한층 복잡하고 불안정하게 한다. 본 논문은 제어기의 시간지연을 고려하여 제안된 제어기의 이득을 설정하는 방법을 제시하고 인버터의 스위칭 주파수와 관련하여 출력측 필터요소의 설계지침을 제시한다. 제안된 설계방법에 의하여 전디지털화(Full Digital Control) 된 DVR 시스템을 제작하여 이론을 검증한다.

Joint Time Delay and Angle Estimation Using the Matrix Pencil Method Based on Information Reconstruction Vector

  • Li, Haiwen;Ren, Xiukun;Bai, Ting;Zhang, Long
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제12권12호
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    • pp.5860-5876
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    • 2018
  • A single snapshot data can only provide limited amount of information so that the rank of covariance matrix is not full, which is not adopted to complete the parameter estimation directly using the traditional super-resolution method. Aiming at solving the problem, a joint time delay and angle estimation using matrix pencil method based on information reconstruction vector for orthogonal frequency division multiplexing (OFDM) signal is proposed. Firstly, according to the channel frequency response vector of each array element, the algorithm reconstructs the vector data with delay and angle parameter information from both frequency and space dimensions. Then the enhanced data matrix for the extended array element is constructed, and the parameter vector of time delay and angle is estimated by the two-dimensional matrix pencil (2D MP) algorithm. Finally, the joint estimation of two-dimensional parameters is accomplished by the parameter pairing. The algorithm does not need a pseudo-spectral peak search, and the location of the target can be determined only by a single receiver, which can reduce the overhead of the positioning system. The theoretical analysis and simulation results show that the estimation accuracy of the proposed method in a single snapshot and low signal-to-noise ratio environment is much higher than that of Root Multiple Signal Classification algorithm (Root-MUSIC), and this method also achieves the higher estimation performance and efficiency with lower complexity cost compared to the one-dimensional matrix pencil algorithm.