• Title/Summary/Keyword: Digital time delay

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Development of a Listener Position Adaptive Real-Time Sound Reproduction System (청취자 위치 적응 실시간 사운드 재생 시스템의 개발)

  • Lee, Ki-Seung;Lee, Seok-Pil
    • The Journal of the Acoustical Society of Korea
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    • v.29 no.7
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    • pp.458-467
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    • 2010
  • In this paper, a new audio reproduction system was developed in which the cross-talk signals would be reasonably cancelled at an arbitrary listener position. To adaptively remove the cross-talk signals according to the listener's position, a method of tracking the listener position was employed. This was achieved using the two microphones, where the listener direction was estimated using the time-delay between the two signals from the two microphones, respectively. Moreover, room reverberation effects were taken into consideration where linear prediction analysis was involved. To remove the cross-talk signals at the left-and right-ears, the paths between the sources and the ears were represented using the KEMAR head-related transfer functions (HRTFs) which were measured from the artificial dummy head. To evaluate the usefulness of the proposed listener tracking system, the performance of cross-talk cancellation was evaluated at the estimated listener positions. The performance was evaluated in terms of the channel separation ration (CSR), a -10 dB of CSR was experimentally achieved although the listener positions were more or less deviated. A real-time system was implemented using a floating-point digital signal processor (DSP). It was confirmed that the average errors of the listener direction was 5 degree and the subjects indicated that 80 % of the stimuli was perceived as the correct directions.

A High Speed and Low Jitter PLL Clock generator (고속 저잡음 PLL 클럭 발생기)

  • Cho, Jeong-Hwan;Chong, Jong-Wha
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.3
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    • pp.1-7
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    • 2002
  • This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

Electrical Characteristic of Power MOSFET with Zener Diode for Battery Protection IC

  • Kim, Ju-Yeon;Park, Seung-Uk;Kim, Nam-Soo;Park, Jung-Woong;Lee, Kie-Yong;Lee, Hyung-Gyoo
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.1
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    • pp.47-51
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    • 2013
  • A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

A study on the core technologies for industrial type digital 3D SFF system

  • Kim, Dong-Soo;An, Young-Jin;Kim, Sung-Jon;Choi, Byung-Oh;Lim, Hyun-Eui
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2170-2174
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    • 2005
  • Selective Laser Sintering (SLS) is a useful rapid prototyping technique for the manufacture of three dimensional (3D) solid objects directly from a scanning data. A new approach called a Selective Multi-Laser Sintering (SMLS) system has been developed at Korea Institute Machinery & Materials (KIMM) as an industrial type SFFS. This SMLS machine is built with a frame, heaters, nitrogen supply part, laser system. This system uses the dual laser and 3D scanner made in $Solutionix^{TM}$ to improve the precision and speed for large objects. The three-dimensional solid objects are made of polyamide powder. The investigation on each part of SMLS system is performed to determine the proper theirs design and the effect of experimental parameters on making the 3D objects. The temperature of the system has a great influence on sintering the polymer. Because the stability of the powder temperature prevents the deformation of each layer, the controls of the temperature in both the system and the powders are very important during the process. Therefore, we simulated the temperature distribution of build room using the temperature analysis with ANSYS program. Selected radiant heater is used to raise temperature of powder to melting point temperature. The laser parameters such as scan spacing, scan speed, laser power and laser delay time affect the production the 3D objects too. The combination of the slow scan speed and the high laser power shows the good results without the layer curling. The work is under way to evaluate the effect of experimental parameters on process and to produce the various objects. We are going to experiment continuously to improve the size accuracy and surface roughness.

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A New Survivor Path Memory Management Method for High-speed Viterbi Decoders (고속 비터비 복호기를 위한 새로운 생존경로 메모리 관리 방법)

  • 김진율;김범진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.5C
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    • pp.411-421
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    • 2002
  • In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.

Flexible, Extensible, and Efficient VANET Authentication

  • Studer, Ahren;Bai, Fan;Bellur, Bhargav;Perrig, Adrian
    • Journal of Communications and Networks
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    • v.11 no.6
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    • pp.574-588
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    • 2009
  • Although much research has been conducted in the area of authentication in wireless networks, vehicular ad-hoc networks (VANETs) pose unique challenges, such as real-time constraints, processing limitations, memory constraints, frequently changing senders, requirements for interoperability with existing standards, extensibility and flexibility for future requirements, etc. No currently proposed technique addresses all of the requirements for message and entity authentication in VANETs. After analyzing the requirements for viable VANET message authentication, we propose a modified version of TESLA, TESLA++, which provides the same computationally efficient broadcast authentication as TESLA with reduced memory requirements. To address the range of needs within VANETs we propose a new hybrid authentication mechanism, VANET authentication using signatures and TESLA++ (VAST), that combines the advantages of ECDSA signatures and TESLA++. Elliptic curve digital signature algorithm (ECDSA) signatures provide fast authentication and non-repudiation, but are computationally expensive. TESLA++ prevents memory and computation-based denial of service attacks. We analyze the security of our mechanism and simulate VAST in realistic highway conditions under varying network and vehicular traffic scenarios. Simulation results show that VAST outperforms either signatures or TESLA on its own. Even under heavy loads VAST is able to authenticate 100% of the received messages within 107ms. VANETs use certificates to achieve entity authentication (i.e., validate senders). To reduce certificate bandwidth usage, we use Hu et al.'s strategy of broadcasting certificates at fixed intervals, independent of the arrival of new entities. We propose a new certificate verification strategy that prevents denial of service attacks while requiring zero additional sender overhead. Our analysis shows that these solutions introduce a small delay, but still allow drivers in a worst case scenario over 3 seconds to respond to a dangerous situation.

Hardware design of Reed-solomon decoder for DMB mobile terminals (DMB 휴대용 단말기를 위한 Reed-Solomon 복호기의 설계)

  • Ryu Tae-Gyu;Jeong Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.4 s.346
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    • pp.38-48
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    • 2006
  • In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.

A Voltage Disturbance Detection Method for Computer Application Lods (컴퓨터 응용 부하들을 위한 전압 외란 검출 방법)

  • 이상훈;최재호
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.6
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    • pp.584-591
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    • 2000
  • Power Quality Compensator(PQC) has been installed to protect the sensitive loads against the voltage disturbances, such as voltage sag and interruption. In general, static switch is used for the purpose of link between utility and PQC. So transfer operation of the static switch play a important part in the PQC. Many studies on the structure and control of PQC have been progressed in active, but these researches have been rarely mentioned about any voltage-disturbances-detection method to start the PQC operation. In this paper, a new voltage-disturbances-detection algorithm for computer application loads using the CBEMA/ITIC curve is proposed for transfer operation of the static switch. The proposed detection algorithm is implemented to get fast detecting time through the comparison of instantaneous 3-phase voltage values transferred to DC values in the synchronous reference frame with the operating reference values. To get the robust characteristics against the noise, a first order digital filter is designed. The magnitude falling and phase delay caused by the filter are compensated through the error normalizing and numerical analysis using transfer function, respectively. Finally, the validity of the proposed algorithm is proved by ACSL simulation and experimental results.

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Accuracy Improvement for Building Inundation Trace Map using Accurate DEM Data and Flood Damage Information (정밀지형자료와 과거 침수피해정보를 활용한 침수흔적도 구축 정확도 개선)

  • Goo, Sin-Hoi;Kim, Seong-Sam;Park, Young-Jin;Choi, Jae-Won
    • Journal of Korean Society for Geospatial Information Science
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    • v.19 no.4
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    • pp.91-99
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    • 2011
  • With increasing astronomically damage costs caused by frequent and large-sized flood, a hazard map containing comprehensive analysis results such as inundation trace investigation, flood possibility analysis, and evacuation plan establishment for flooded regions is a fundamental measure of non-structural flood prevention. Though an inundation trace map containing flood investigation results occurred by typhoon, rainfall and tsunami is a basic hazard map having close relationship with a flood possibility map as well as a hazard information map, it is often impossible to be produced because of financial deficiency, time delay of investigation, and the lack of maintenance for flood traces. Therefore, this study proposes the accuracy enhancement procedure of inundation trace map with flood damage information and three-dimensional Digital Elevation Model (DEM) for the past frequent flooded regions according to a guideline for inundation trace map of National Emergency Management Agency (NEMA).

Non-contact Detection of Ultrasonic Waves Using Fiber Optic Sagnac Interferometer (광섬유 Sagnac 간섭계를 이용한 초음파의 비접촉식 감지)

  • Lee, Jeong-Ju;Jang, Tae-Seong;Lee, Seung-Seok;Kim, Yeong-Gil;Gwon, Il-Beom;Lee, Wang-Ju
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.25 no.9
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    • pp.1400-1409
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    • 2001
  • This paper describes a fiber optic sensor suitable for non-contact detection of ultrasonic waves. This sensor is based on a fiber optic Sagnac interferometer. Quadrature phase bias between two interfering laser beams in Sagnac loop is introduced by a polarization controller. A stable quadrature phase bias can be confirmed by observing the interferometer output versus phase bias. This method eliminates a digital signal processing for detection of ultrasonic waves using Sagnac interferometer. Interference intensity is affected by the frequency of ultrasonic waves and the time delay of Sagnac loop. Collimator is attached to the end of the probing fiber to focus the light beam onto the specimen surface and to collect the reflected light back into the fiber probe. Ultrasonic waves produced by conventional ultrasonic transducers are detected. This fiber optic sensor based on Sagnac interferometer is very effective for detection of small displacement with high frequency such as ultrasonic waves used in conventional non-destructive testing.