• ETRI Journal
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• 제19권3호
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• 대한전자공학회논문지SD
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• 제44권9호
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• pp.54-58
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• 2007

LTPS TFT의 개발과 성능 향상은 패널에 다양한 디지털 회로를 내장하는 SOP의 비약적 발전에 기여하였다. 본 논문에서는 일반적으로 적용되는 낮은 성능의 CMOS 논리게이트를 대체할 수 있는 전류모드 논리(CML) 게이트의 설계 방법을 소개한다. CML 인버터는 낮은 로직스윙, 빠른 응답 특성을 갖도록 설계할 수 있음을 보였으며 높은 소비전력의 단점도 동작 속도가 높아질수록 CMOS의 경우와 근사해졌다. 아울러 전류 구동능력을 키울 필요가 없는 까닭에 많은 수의 소자가 사용되지만 면적은 오히려 감소하는 것을 확인하였다. 특히 비반전 및 반전 출력이 동시에 생성되므로 noise immunity가 우수하다. 다수 입력을 갖는 NAND/AND 및 NOR/OR 게이트는 같은 회로에 입력신호를 바꾸어 구현할 수 있고 MUX와 XNOR/XOR 게이트도 같은 회로를 사용하여 구현할 수 있음을 보였다. 결론적으로 CML 게이트는 다양한 함수를 단순한 몇가지의 회로로 구성할 수 있으며 낮은 소비전력, 적은 면적, 개선된 동작속도 등을 동시에 추구할 수 있는 대안임을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.903-906
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• 2008

We developed the advanced LTPS (A-LTPS) manufacturing process. The a-Si TFT process was combined with selectively enlarging laser crystallization (SELAX) technology to improve the carrier mobility in the region where the peripheral circuits are to be fabricated. A 2.4-inch IPS-pro LCD panel for personal digital assistant use was successfully fabricated using the developed technology.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2003년도 춘계학술발표논문집
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• pp.208-210
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• 2003

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor fer a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.333-340
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• 2017

In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

• ETRI Journal
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• 제30권5호
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• 전자공학회논문지C
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• 제34C권5호
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• pp.1-17
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• 1997

With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.55-60
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• 2011

그동안 신경망칩의 설계에는 주로 아날로그 Maximum Selector (MS) 회로를 사용하였다. 그러나 집적도가 높아질수록 아날로그 MS회로는 신호의 해상도(Resolution)을 높이는데 어려움이 있다. 반면 디지털 MS 회로는 높은 해상도를 얻기는 쉬우나 속도가 느린 단점이 있었다. 본 논문에서는 신경망칩의 디지털화에 사용하기 위한 MSIT(Maximum Selector with Internal Trigger-Signal) 라는 고속의 디지털 MS회로를 개발하였다. MSIT는 제어신호 발생기를 내장하여 안정적인 동작을 확보하고, 불필요한 대기시간을 없애도록 이를 최적화 함으로써 높은 속도를 얻을 수 있다. 1.2V-$0.13{\mu}m$ 프로세스의 모델파라메터를 사용하여 32 개의 10 비트 데이터에 대하여 시뮬레이션을 수행한 결과 3.4ns의 응답시간을 얻을 수 있었다. 이는 동급의 해상도를 갖는 아날로그 MS회로 보다 훨씬 빠른 속도로써, MSIT와 같은 디지털 MS 회로가 아날로그 MS회로에 비하여 높은 해상도와 빠른 속도를 구현할 수 있음을 보여준다.

• 한국항행학회논문지
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• 제25권5호
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• pp.363-369
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• 2021

본 논문에서는 텔레메트리 시스템을 위한 가변 컷 오프 주파수 및 가변 샘플레이트 특성을 지니는 저면적 다채널 디지털 필터구조를 제안한다. 제안하는 디지털 필터는 임의의 컷 비율에 대해 필터 뱅크의 추가적인 설계 없이 컷 오프 주파수와 샘플레이트를 가변적으로 사용할 수 있는 필터 뱅크를 구현함으로써 하드웨어 면적을 줄일 수 있었다. 또한, 멀티플렉서 (MUX; Multiplexer) 컨트롤을 통해 통과하는 필터의 개수에 따라 샘플레이트를 가변적으로 선택할 수 있는 구조를 제안한다. 제안하는 디지털 필터는 Quartus의 FIR (finite impulse response) IP (intellectual property)의 TDM (time division multiplexing)을 이용함으로써, TDM을 사용하지 않았을 때보다 면적이 큰 DSP (digital signal processing) 블록을 80개에서 1개로 줄일 수 있었다. Kaiser 창 함수를 이용하여 Matlab을 통해 필터의 차수와 계수를 계산하였으며, VHDL (very high speed integrated circuits hardware description language)을 통해 하드웨어로 구현하였다. 텔레메트리 시스템에 적용 후, 실험 결과를 통해 제안하는 디지털 필터가 정상적으로 동작하고 있음을 확인하였다.