Browse > Article
http://dx.doi.org/10.5573/JSTS.2017.17.3.333

Energy-efficient Reconfigurable FEC Processor for Multi-standard Wireless Communication Systems  

Li, Meng (Interuniversity Microelectronics Center (IMEC))
der Perre, Liesbet Van (Department of Electrical Engineering, KU Leuven)
van Thillo, Wim (Interuniversity Microelectronics Center (IMEC))
Lee, Youngjoo (Department of Electrical Engineering, POSTECH)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.17, no.3, 2017 , pp. 333-340 More about this Journal
Abstract
In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.
Keywords
Digital integrated circuits; error correction codes; programmable circuits; wireless communication;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 Multiplexing and Channel Coding, 3GPP TS 36.212, Rev. 11.3.0, Jun. 2013.
2 IEEE Standard for Local and metropolitan area networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems, IEEE Std 802.16e-2005, 2006.
3 IEEE Standard for Information Technology-Telecommunications and Information Exchange between Local and Metropolitan Area Networks-Specific Requirements-Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Std 802.11n- 2009, 2009.
4 W. Byun, H. Kim, and J.-H. Kim, "High throughput radix-4 SISO decoding architecture with reduced memory requirement," J. Semicon. Technol. Sci., vol. 14, no. 4, pp. 407-418, Aug. 2014.   DOI
5 F. Naessens et al., "A $10.37mm^2$ 675 mW reconfigurable LDPC and turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE," in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 213-214.
6 Y.-M. Jung, C.-H. Chung, Y.-H. Jung, and J.-S. Kim, "7.7 Gbps encoder design for IEEE 802.11ac QC-LDPC Codes," J. Semicond. Technol. Sci., vol. 14, no. 4, pp. 419-426, Aug. 2014.   DOI
7 C. Condo, M. Martina, and G. Masera, "VLSI implementation of a multi-mode turbo/LDPC decoder architecture," IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 60, no. 6, pp. 1441-1454, June 2013.   DOI
8 Z. Wu and D. Liu, "Flexible multistandard FEC processor design with ASIP methodology," in Proc. IEEE Int. Conf. Application-specific Systems, Architectures and Processors (ASAP), 2014, pp. 210-218.
9 B. Noethen et al., "A 105GOPS $36mm^2$ heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detectiondecoding for 4G in 65nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2014, pp. 188-189.
10 P. Murugapp, R. Al-Khayat, A. Baghdadi, and M. Jezequel, "A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding," in Proc. Design, Automation Test in Europe Conf. Exhib. (DATE), 2012, pp. 1525-1530.
11 Z. Wu, D. Liu, Z. Yang, Q. Wang, and W. Zhou, "FPGA implementation of a multi-algorithm parallel FEC for SDR platforms," in Proc. IEEE Int. Conf. Field Programmable Logic and Applications (FPL), 2014, pp. 1-6.
12 S. Kunze, E. Matus, G. Fettweis, and T. Kobori, "Combining LDPC, turbo and Viterbi decoders: Benefits and cost," in Proc. Int. Workshop on Signal Process. Syst. (SiPS), 2011, pp. 216-221.
13 J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, San Mateo, CA, USA: Morgan Kaufmann, 2011.
14 J. Dion, M. Hamon, P. Penard, M. Arzel and M. Jezequel, "Multi-standard trellis-based FEC decoder," in Proc. IEEE Conf. Design and Architectures for Signal and Image Processing (DASIP), 2012, pp. 1-7.