• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.261-268
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• 2014

This paper presents a electrocardiogram(ECG), electromyogram(EMG), and Photoplethysmography(PPG) signal wireless monitoring system based on Bluetooth Low Energy (BLE). ECG and EMG sensor interface analog front-end circuits are designed by using off-the-shelf parts. Texas Instruments(TI)'s CC2540DK is used for BLE-based communication. Two CC2540DK modules are used as Peripheral and Central nodes. In peripheral device, vital signals are acquired by the analog front-ends and fed to ADC for analog-to-digital conversion. The peripheral transmitts the data through the air to the central device. The central device receive the data and sends them to PC using UART. GUI is designed using Labview for displaying the acquired vital signals. The developed system can be used for future ubiquitous wireless healthcare system based on bluetooth 4.0.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.1
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• pp.9-15
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• 2008

A new ECT probe to separate the ECT signal distortion due to PVC (permeability variation clusters) and ordinary defects created in SG tubes has been developed. The hystersis loops of PVC which are extracted from retired SG (steam generator) tubes of Kori-1 NNP were measured. The tensile tests were performed to identify the mechanism of PVC creation. The conditions detecting the PVC created in 56 tubes were investigated using computer simulation, and the signal processing circuits were inserted in the probe for the digital signal transmission. The new Probe can measure and separate the PVC signal which is created in the SG tubes, and also measures the defects in Ni-sleeving part of SG tubes. furthermore the new ECT probe can measure the defects as fast as bobbin probe, and enhance the testing speed as well as reliability of the defect detection of SG tubes.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.36-44
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• 2015

This paper proposes a low-complexity processor to correct vignetting and barrel distortion for wide-angle cameras. The proposed processor calculates the required correcting factors by employing the piecewise linear approximation so that the hardware complexity can be reduced significantly while maintaining correction quality. In addition, the processor is designed to correct the two distortions concurrently in a singular pipeline, which reduces the overall complexity. The proposed processor is implemented with 18.6K logic gates in a $0.11{\mu}m$ CMOS process and shows the maximum correction speed of 200Mpixels/s for correcting an image of which size is $2048{\times}2048$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.103-109
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• 2007

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.18-27
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• 2004

In this paper, we presents an analytical simulation procedure for evaluation in baseband digital modulated signals distortions in the present of RF power amplifier(SSPA) nonlinear behavior and backoff operations of OFDM wireless transmission system. we obtained the optimum nonlinear transfer function of designed SSPA with the SiGe HBT bias currents of OFDM multi-channel wireless transmission system and compared this transfer function to SSPA nonlinear modeling functions mathematically, we finds optimum bias conditions of designed SSPA. With the derived nonlinear modeling function of SSPA, We analysed the PSD characteristics of in-band and out-band output powers of SSPA EVM measurement results of distorted constellation signals with the input power levels of SSPA. The results of paper can be applied to find the SSPA linearly with optimum bias currents and determine the SSPA input backoff bias for AGC control circuits of SSPA.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.2
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• pp.97-104
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• 2004

As a device that returns surplus energy, regenerated from trains to d.c. source, to a.c. system and reuses it, the thyristor Inverter has been widely used. Because the conventional thyristor inverter is a unidirectional phase-controlled device, it Is Impossible to control the power factor of its output. Moreover, harmonics emission is high and it needs to take a additional filter. In this paper, to solve the problems stated above, the inverter, which can control real and reactive power by adopting IGBT modules as switching elements and being controlled by means of space vector PWM, is developed. Considering high economical efficiency and reliability in order to apply to the system for commercial use, the developed inverter is equipped with fully digital control system and low pass filter, and reduces harmonics and has compact size. The detail description about the developed inverter is stated in various respects: design criteria, technical description, power circuits, control techniques, the developed system, test results, etc.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.