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FSM Designs with Control Flow Intensive Cycle-C Descriptions  

Yun Chang-Ryul (충남대학교 컴퓨터공학과)
Jhang Kyoung-Son (충남대학교 컴퓨터공학과)
Publication Information
Journal of KIISE:Computing Practices and Letters / v.11, no.1, 2005 , pp. 26-35 More about this Journal
Abstract
Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.
Keywords
FSM; Cycle-C; control flow intensive; controller; state diagram;
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