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A Design Procedure of Digitally Controlled Oscillator for Power Optimization  

Lee, Doo-Chan (Dep. of Nano Semiconductor Eng., Korea University)
Kim, Kyu-Young (Dep. of Electrical Eng., Korea University)
Kim, Soo-Won (Dep. of Electrical Eng., Korea University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.5, 2010 , pp. 94-99 More about this Journal
Abstract
This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.
Keywords
Digitally controlled oscillator(DCO); All-digital phased locked loop(ADPLL); Clock generator;
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