• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.391-397
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• 1994

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16R4, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.38-49
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• 1994

This paper proposes Echo canceller used in simultaneous two-way ('full-duplex') transmission of data signals over two-wire circuits which can be achieved by using a hybrid coupler. This Echo canceller uses sequential processing instead of parallel processing with conventional adaptive digital filter. This structure reduces the number of multipliers. Thus, this structure is much more suitable for IC implementation. This Echo canceller operates according to the 'Stochastic Iteration Algorithm(SIA).' SIA algorithm has merit of good performance and small hardware requirement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.9
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• pp.951-962
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• 1992

The layout of electrical power distribution networks never involved communications aspects. As a result their transmission properties severly complicate the use as data links. Futhermore bandwidth as well as transmission power is restricted. Nevertheless, power distribution net works represent a most attractive medium for digital communication purposes due to an ever increasing demand, e.g., for environment management of buildings, office automation, and remote meter reading or security monitoring. In this paper, a power line modem which is capable of transmitting and receiving data at 1200 bps using OOK-BASK through 220V AC power lines is implemented. The receiver includes noncoherent detector and performs soft decision. The OLM circuits can be simplified by use of microprocessor. The PLM also satisfies CENELEC, European standards, and can be applied to home automation system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.90-95
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• 2007

Chaotic OOK(On-Off Keying) modulation method can be used in LDR(Low Data Rate) UWB systems. The chaotic generator in one of the most important circuit in this system. The traditional chaotic generator circuits using analog feed back technique have low yield characteristic due to the process variation. A novel quasi-chaotic signal generator using digital PN-sequence in proposed in this paper and verified in 0.18um CMOS teleology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.231-239
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• 1998

In this paper, we designed a current controlling servo system for speed control of a PMSM. In existing auto-tuning methods for PI controller parameters, the output response is delayed and the overshoot is generated. By solving these existing problems in this paper, a new PI auto-tuning method is applied to the speed controller for fast-response and reduced overshoot. PMSM servo systems offer a great advantage in unmanned factories where a great number of servo motors are employed, because of its easy maintenance characteristics and controllability. The implemented servo system is composed of absolute position detecting circuits of a rotor, a new auto-tuning PI control algorithm, a speed controller by using DSP, and power driving section. The proposed servo system is verified for it's practical availability by considering experimental results.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.24-25
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• 2017

In this paper, a low cost bridgeless interleaved power factor correction topology for electric vehicle charger application is proposed. With the proposed topology the number of switches, inductors, current sensors and associated circuits can be reduced, thereby reducing the cost of the system as compared to the conventional bridgeless PFC circuit. The reduced input current ripple by the proposed interleaved topology makes it suitable for high power applications such as electric vehicle chargers since it can reduce the size of the inductor core and the Electro Magnetic Interference (EMI) problem. In the proposed topology only one current sensor is required. All the boost inductor currents can be reconstructed by sampling the output current and used to control the input current. Therefore the typical problem caused by the unequal current gain of each current sensor inherently does not exist in the proposed topology. In addition the current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. The performance of the proposed converter is verified by the experimental results with a prototype of 6.6kW bridgeless interleaved PFC circuit.

• Bulletin of the Korean Space Science Society
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• 1993.10a
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• pp.21-21
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• 1993

The imaging areas of currently available optical detectors are relatively small to cope with large image areas such as telescope focal Planes. One Possibility to obtain large detection areas is to assemble mosaics of Charge Coupled Devices(CCDs) and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however such optimisation is very important when the ultimate low light level performance is required particularly for new devices. In this work, a new concept has been developed for an entirely novel approach where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The controller has been designed to include one electronic of component produced by CAD software where most of the digital circuits are integrated to minimise the component count and improve the efficiency of the system greatly. The software has an open architecture to permit convenient modificationl by the user to fit their specific purposes. The desire of controller allows great flexibility of system parameters by the softwa re, specifically for the compatibility to deal with any number of mixed CCDs and in any format within the practical limit. The system has been integrated to test the performance and the result is discussed for readout noise, system linearity and cross-talk between the CCDs. The system developed in this work can be applicable not only for astro nomical observation with a telescope but also in other related fields for low light level detection systems such as spectroscopic application, remote sensing and X-ray detecti13n systems with large sensing areas and high resolution.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.