• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.79-83
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• 2004

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

• Journal of Power Electronics
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• v.11 no.2
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.291-296
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• 2015

Transmission line is exposed to a large area, and then faults are likely to occur than the other component of power system. When a fault occurs on a transmission line, fault locator helps fast recovery of power supply on power system. This paper deals with the design of a digital fault locator for improvement accuracy of the fault distance estimation and a fault occurrence position for transmission line. The algorithm of a fault locator uses a DC offset removal filter and DFT filter. The algorithm utilizes a fault data of GPS time synchronized. The computed fault information is transmitted to the other side substation through communication. The digital fault locator includes MPU module, ADPU module, SIU module, and a power module. The MMI firmware and software of the fault locator was implemented.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.319-322
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• 2005

This paper describes practical tuning methods and testing of a digital PSS, which uses both frequency and power, with the 220MVA Chungpyung P/P #1 in the KEPCO system to enhance the damping of local modes. In the first step, the objective phase of PSS is computed through a phase leading function to provide compensation between the exciter reference point and the generator air-gap torque before tuning the PSS's time constants. In addition, eigenvalue analysis was used to determine a range of PSS's gain, whichis the more useful for field testing rather than a single gain value. The Real-Time Digital Simulator was used to verify safe operations of the PSS in the presence of disturbances, such as AVR step and three phase fault.

• Journal of Power Electronics
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• v.17 no.1
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• pp.1-10
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• 2017

This paper presents a novel predictive digital control method for boundary conduction mode PFC converters without the need for detecting the inductor current. In the proposed method, the inductor current is predicted by analytical equations instead of being detected by a sensing-resistor. The predicted zero-crossing point of the inductor current is determined by the values of the input voltage, output voltage and predicted inductor current. Importantly, the prediction of zero-crossing point is achieved in just a single switching cycle. Therefore, the errors in predictive calculation caused by parameter variations can be compensated. The prediction of the zero-crossing point with the proposed method has been shown to have good accuracy. The proposed method also shows high stability towards variations in both the inductance and output power. Experimental results demonstrate the effectiveness of the proposed predictive digital control method for PFC converters.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.127-130
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• 2000

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.

• Journal of Power Electronics
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• v.15 no.3
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• pp.644-651
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• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.12
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• pp.611-623
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• 2002

This paper introduce the real time digital simulator which is located in Korea Electric Power Research Institute. This paper also describes the methodology for the performance test of the PSS using KEPS. This test is to get a high degree of the confidence of the developed PSS before it is installed into the real power system. This has been performed in the form of closed-loop tests in which Simulator and PSS are connected and signals come and back interactively. Many tests have successfully done using KEPS which consists of 26 RTDS racks, under the large-scale power system. The simulated reduced KEPCO power system contains 88 generators and 295 buses. Through the AVR step, three phase fault and active power variation test, the effectiveness of developed PSS has been proved. This paper also presents the overview of KEPS and hardware of protype PSS.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.529-533
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• 1993

Recently, the analysis of power systems is transfering from analytical techniques to simulation because it is difficult to analyze accurately the phenomena occured in complicated and huge power systems. Digital computers are used popularly to analyze the phenomena of power systems. But real-time simulators were used due to the limitation of digital computer - real time analysis, non-linearity and so on - and rapid development of digital technologies. In this paper, we discuss the advanced foreign power system simulators and the conceptual designs for the KEPCO power system simulator have been drawn for the domestic development.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.27-33
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• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.