• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.423-423
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• 2004

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.1
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• pp.55-63
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• 2013

Digital retrodirective antenna system is easy to modify and upgrade because it can control the phase information of the output signal toward opposite direction to input signal without a priori knowledge of the arrival direction. Due to this advantage, it is possible to do fast beam tracking. Especially, we need to design the digital PLL performance for the digital retrodirective array antenna system. So, in this paper the settling time of phase estimator and BER performance of retrodirective antenna system are investigated according to design of filter in digital PLL. When QAM signal is used for 1 Mbps with $30^{\circ}$ of phase delay, simulation results show that digital phase conjugation technique has better BER performance by about 1 dB than non-phase conjugation system when digital filter is stable. If not, the system can't estimate the exact phase because of oscillation of filter.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.874-877
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• 1987

In this paper a DPLL circuit realizable by digital IC's is propose and the principles of general DPLL are described. An all Digital phase locked loop is designed, analyzed, and tested. In particular, the approach of invoking Gaussian assumption on the decision variable and based on S.O.Rices theory is used. As a performance of the above PLL detector operating on low data rate FSK is given and demonsrtated to be FSK reception.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.45-53
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• 1996

In this paper, the convergence behavior of timing phase when an adaptive partial response equalizer and decision-directed type of a PLL work together in a digital recording channel is described. The phenomena of getting biased in timing phase when the convergence parameter of an adaptive partial response equalizer and timing recovery constant of a PLL are not selected properly is introduced. The phenomena, occurring due to perturbation of timing phase, are analyzed, by computer simulation and the region of ocnvergence for timing phase is discussed. Also, a method to overcome the phenomena using a variable step-size parameter is described.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.893-899
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• 2008

Behavioral level simulations of LDO voltage regulator and phase locked loop(PLL) are performed with CPPSIM, a behavioral-level simulation tool based on C language. The validity of the simulation tool is examined by modeling analog circuits and simulating the circuits. In addition, the designed PLL adopted digital architecture to possess advantages of digital circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.809-815
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• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.91-93
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• 2008

In this paper, novel phase angle following algorithm for the single phase grid-connected inverter is proposed. Gird-connected inverter needs phase angle detection for synchronization grid voltage with the inverter output. In case of single phase grid-connected inverter, zero crossing detection and virtual 2-phase PLL using digital all pass filter or digital low pass filter are used conventionally. But these methods have a weakness for harmonics, noises and ripples. The proposed method of PLL achieve DFT(Discrete Fourier Transform) using Goertzel algorithm. It can extract fundamental voltage of grid. As a results, it can obtain phase angle using digital all pass filter without effect of harmonics, noises and ripples. Simulation results are presented to demonstrate the effectiveness of the proposed algorithm.