• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.492-499
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• 1997

We proposed and studied an all-optical switching device made of a bent nonlinear waveguide and an all-optical logic gate made of a bent nonlinear Y-junction. The proposed devices as switch and a logic function are based on the evolution of nonlinear guided wave along a bent nonlinear waveguide. Since the characteristics of beam propagation depens on the nonlinearity, input power and bent angle of waveguide, the characteristics of output power transmission is calculated by variation the such parameters. Furthermore, by calculating the output power through the nonlinear media with different positions of detector in nonlinear media, we could find the ideal digital switching performance at specific position of detector and implement several all-optical logic functions (AND, OR, XOR) by power contrast between waveguide end and nonlinear media.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.397-399
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• 2017

The HDB3 code, a type of line code, is a data coding method used for digital data transmission. It is used to remove the DC wander on the transmission line which occurs when the DC component data is transmitted continuously. The military tactical communication network uses HDB3 code for data transmission and develops equipment using commercial HDB3 Codec IC. Because it is operated for more than 10 years due to the characteristics of military equipment, if a failure occurs in the equipment, the equipment can not be repaired due to the discontinuance of the part, so that the entire equipment may not be used. In this paper, we implement the HDB3 Codec as a logic to solve this problem and verify that the performance is equivalent to that of commercial parts.

• Journal of Internet of Things and Convergence
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• v.4 no.1
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• pp.1-5
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• 2018

This paper is concerned with the modeling and identification of time series data corrupted by noise. As modeling techniques, nonsingleton fuzzy logic system (NFLS) is employed for the modeling of corrupted time series. Main characteristic of the NFLS is a fuzzy system whose inputs are modeled as fuzzy number. So the NFLS is especially useful in cases where the available training data or the input data to the fuzzy logic system are corrupted by noise. Simulation results of the Mackey-Glass time series data will be demonstrated to show the performance of the modeling methods. As a result, NFLS does a much better job of modeling noisy time series data than does a traditional Mamdani FLS.

• Fire Science and Engineering
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• v.11 no.2
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• pp.45-53
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• 1997

In this article, the Fuzzy Logic as the principle of the multcriteria fire detector is used to determine whether the fire takes out or not. The main contents of this method as follow; most of all, the degree of the fire is represented as the type of the Fuzzy, and then it is possible to examine whether the fire takes out or not by the principle of the Fuzzy Logic. The input fators of the Fuzzy fire detector are temperature sensor, smoke sensor, light sensor applied to digital type. On the result of this study, the first, the number of the case of the nonfire alarm which is represented in the existing fire detector is reduced, and the second, the applicability of the fuzzy detector is demonstrated by the test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.