• Title/Summary/Keyword: Digital Logic

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Electrical Characteristics of CMOS Circuit Due to Channel Region Parameters in LDMOSFET

  • Kim, Nam-Soo;Cui, Zhi-Yuan;Lee, Hyung-Gyoo;Kim, Kyoung-Won
    • Transactions on Electrical and Electronic Materials
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    • v.7 no.3
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    • pp.99-102
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    • 2006
  • The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

Design of A High-Speed Data Transmission System for Satellite Ground Inspection Trial

  • Hao Sun;Dae-Ki Kang
    • International journal of advanced smart convergence
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    • v.12 no.4
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    • pp.26-34
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    • 2023
  • A high-speed data transmission system is designed for the ground inspection equipment of satellite measurement and control. Based on USB2.0, the system consists of interface chip CY7C68013A, programmable logic processing unit EP4CE30F23C8, analog/digital and digital/analog conversion units. The working principle of data transmission is analyzed, and the system software logic and hardware composition scheme are detailed. The system was utilized to output/capture and store specific data packets. The results show that the high-speed data transmission speed can reach 38MB/s, and the system is effective for satellite test requirements.

Hybrid Type Structure Design and DLT-Replacement Circuit of the High-Speed Frequency Synthesizer (고속 스위칭 동작의 주파수 합성기를 위한 하이브리드형 구조 설계와 DLT 대체 회로 연구)

  • Lee Hun-Hee;Heo Keun-Jae;Jung Rag-Gyu;Ryu Heung-Gyoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.12 s.91
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    • pp.1161-1167
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    • 2004
  • The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

Fault Detection through the LASAR Component modeling of PLD Devices (PLD 소자의 LASAR 부품 모델링을 통한 고장 검출)

  • Pyo, Dae-in;Hong, Seung-beom
    • Journal of Advanced Navigation Technology
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    • v.24 no.4
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    • pp.314-321
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    • 2020
  • Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

Chaotic Phenomena in Addiction Model for Digital Leisure

  • Bae, Youngchul
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.13 no.4
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    • pp.291-297
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    • 2013
  • Chaotic dynamics have been studied by many researchers in the fields of biology, physics, and engineering. Interest in chaos is also expanding to the social sciences such as politics, economics, and others, including the prediction of societal events. The concept of leisure has developed from a passive concept correlated with relaxation, entertainment, and ideology formation into a positive concept that assumes a more active role. As information and communications technology develops, digital leisure activity is expected to continue spreading. This expansion of digital leisure function correctly, as well as. Traditional leisure activity functions correctly more, whereas digital leisure activity is predicted to function incorrectly more often. In this paper, we propose a mathematical addiction model of digital leisure that deals with its dysfunctions such as addiction to digital leisure, including computer games, internet search, internet chatting, and social media. Herein, to solve addiction to digital leisure, we propose a model derived from a nicotine addiction.

Development of OPC UA based Smart Factory Digital Twin Testbed System (OPC UA 기반 스마트팩토리 디지털 트윈 테스트베드 시스템 개발)

  • Kim, Jaesung;Jeong, Seok Chan;Seo, Dongwoo;Kim, Daegi
    • Journal of Korea Multimedia Society
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    • v.25 no.8
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    • pp.1085-1096
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    • 2022
  • The manufacturing industry is continuously pursuing advanced technology and smartization as it converges with innovative technology. Improvement of manufacturing productivity is achieved by monitoring, analyzing, and controlling the facilities and processes of the manufacturing site in real time through a network. In this paper, we proposed a new OPC-UA based digital twin model for smart factory facilities. A testbed system for USB flash drive packaging facility was implemented based on the proposed digital twin model and OPC-UA data communication scheme. Through OPC-UA based digital twin model, equipment and process status information is transmitted and received from PLC to monitoring and control 3D digital models and physical models in real time. The usefulness of the developed digital twin testbed system was evaluated through usability test.

LOS/LOC Scan Test Techniques for Detection of Delay Faults (지연고장 검출을 위한 LOS/LOC 스캔 테스트 기술)

  • Hur, Yongmin;Choe, Youngcheol
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.219-225
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    • 2014
  • The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

A New Design of High-Speed 1-Bit Full Adder Cell Using 0.18${\mu}m$ CMOS Process (0.18${\mu}m$ CMOS 공정을 이용한 새로운 고속 1-비트 전가산기 회로설계)

  • Kim, Young-Woon;Seo, Hea-Jun;Cho, Tae-Won
    • Journal of IKEEE
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    • v.12 no.1
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    • pp.1-7
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    • 2008
  • With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

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Application of Fuzzy Logic in Scenario Based Language, Learning (시나리오 기반 언어 학습에서 퍼지논리 적용에 관한 연구)

  • Lee, Sang-Hyun;Moon, Kyung-Il;Lee, Sang-Joon
    • Journal of Digital Convergence
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    • v.11 no.2
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    • pp.221-228
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    • 2013
  • A number of research studies focus on the efficacy of using such as scenario based learning. However, desirable methods have not been introduced to assess the scenario based learning. This article is to suggest a fuzzy logic based framework for scenario base learning in which more reasonable learning effects are measured. It can be solved uncertain problems of linguistic variables. Also, we suggest three measures of accuracy, comprehensibility and completeness in order to evaluate accurate effects of scenario based learning. This assessment provides the scenario to the learner in which the scenario is presented in an authentic context, and enable the learner to reach an outcome through an adequate sequence and choices. This approach enables the system to present new scenarios and outcomes based on what a user selects. In particular, the application of fuzzy logic in scenario based learning can be easily pursued certain successful path or wrong path all the way through to reach major outcome in real situation.